Tilmann Scheller 195dd8a1ce ARM: Default to the Swift CPU when targeting armv7s/thumbv7s. ... Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-02 17:09:01 +00:00
..
AArch64
ARM	ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.	2013-09-02 17:09:01 +00:00
CPP
Generic
Hexagon	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	Make sure we don't generate stubs for any of these functions because they	2013-09-01 04:12:59 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Call support for fast-isel.	2013-08-30 22:18:55 +00:00
R600	R600/SI: Enable local-memory-two-objects lit test	2013-08-27 10:28:26 +00:00
SPARC
SystemZ	[SystemZ] Add support for TMHH, TMHL, TMLH and TMLL	2013-08-28 10:31:43 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2
X86	FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).	2013-09-02 12:00:53 +00:00
XCore