mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bf1118285c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32735 91177308-0d34-0410-b5e6-96231b3b80d8
285 lines
10 KiB
TableGen
285 lines
10 KiB
TableGen
//===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class PPCReg<string n> : Register<n> {
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let Namespace = "PPC";
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}
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// We identify all our registers with a 5-bit ID, for consistency's sake.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// GP8 - One of the 32 64-bit general-purpose registers
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class GP8<GPR Alias> : PPCReg<Alias.Name> {
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field bits<5> Num = Alias.Num;
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let Aliases = [Alias];
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}
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// SPR - One of the 32-bit special-purpose registers
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class SPR<bits<10> num, string n> : PPCReg<n> {
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field bits<10> Num = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// VR - One of the 32 128-bit vector registers
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class VR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<5> num, string n> : PPCReg<n> {
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field bits<5> Num = num;
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}
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// General-purpose registers
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def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
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def R1 : GPR< 1, "r1">, DwarfRegNum<1>;
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def R2 : GPR< 2, "r2">, DwarfRegNum<2>;
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def R3 : GPR< 3, "r3">, DwarfRegNum<3>;
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def R4 : GPR< 4, "r4">, DwarfRegNum<4>;
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def R5 : GPR< 5, "r5">, DwarfRegNum<5>;
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def R6 : GPR< 6, "r6">, DwarfRegNum<6>;
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def R7 : GPR< 7, "r7">, DwarfRegNum<7>;
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def R8 : GPR< 8, "r8">, DwarfRegNum<8>;
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def R9 : GPR< 9, "r9">, DwarfRegNum<9>;
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def R10 : GPR<10, "r10">, DwarfRegNum<10>;
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def R11 : GPR<11, "r11">, DwarfRegNum<11>;
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def R12 : GPR<12, "r12">, DwarfRegNum<12>;
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def R13 : GPR<13, "r13">, DwarfRegNum<13>;
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def R14 : GPR<14, "r14">, DwarfRegNum<14>;
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def R15 : GPR<15, "r15">, DwarfRegNum<15>;
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def R16 : GPR<16, "r16">, DwarfRegNum<16>;
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def R17 : GPR<17, "r17">, DwarfRegNum<17>;
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def R18 : GPR<18, "r18">, DwarfRegNum<18>;
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def R19 : GPR<19, "r19">, DwarfRegNum<19>;
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def R20 : GPR<20, "r20">, DwarfRegNum<20>;
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def R21 : GPR<21, "r21">, DwarfRegNum<21>;
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def R22 : GPR<22, "r22">, DwarfRegNum<22>;
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def R23 : GPR<23, "r23">, DwarfRegNum<23>;
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def R24 : GPR<24, "r24">, DwarfRegNum<24>;
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def R25 : GPR<25, "r25">, DwarfRegNum<25>;
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def R26 : GPR<26, "r26">, DwarfRegNum<26>;
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def R27 : GPR<27, "r27">, DwarfRegNum<27>;
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def R28 : GPR<28, "r28">, DwarfRegNum<28>;
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def R29 : GPR<29, "r29">, DwarfRegNum<29>;
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def R30 : GPR<30, "r30">, DwarfRegNum<30>;
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def R31 : GPR<31, "r31">, DwarfRegNum<31>;
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// 64-bit General-purpose registers
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def X0 : GP8< R0>, DwarfRegNum<0>;
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def X1 : GP8< R1>, DwarfRegNum<1>;
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def X2 : GP8< R2>, DwarfRegNum<2>;
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def X3 : GP8< R3>, DwarfRegNum<3>;
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def X4 : GP8< R4>, DwarfRegNum<4>;
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def X5 : GP8< R5>, DwarfRegNum<5>;
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def X6 : GP8< R6>, DwarfRegNum<6>;
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def X7 : GP8< R7>, DwarfRegNum<7>;
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def X8 : GP8< R8>, DwarfRegNum<8>;
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def X9 : GP8< R9>, DwarfRegNum<9>;
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def X10 : GP8<R10>, DwarfRegNum<10>;
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def X11 : GP8<R11>, DwarfRegNum<11>;
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def X12 : GP8<R12>, DwarfRegNum<12>;
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def X13 : GP8<R13>, DwarfRegNum<13>;
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def X14 : GP8<R14>, DwarfRegNum<14>;
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def X15 : GP8<R15>, DwarfRegNum<15>;
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def X16 : GP8<R16>, DwarfRegNum<16>;
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def X17 : GP8<R17>, DwarfRegNum<17>;
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def X18 : GP8<R18>, DwarfRegNum<18>;
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def X19 : GP8<R19>, DwarfRegNum<19>;
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def X20 : GP8<R20>, DwarfRegNum<20>;
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def X21 : GP8<R21>, DwarfRegNum<21>;
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def X22 : GP8<R22>, DwarfRegNum<22>;
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def X23 : GP8<R23>, DwarfRegNum<23>;
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def X24 : GP8<R24>, DwarfRegNum<24>;
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def X25 : GP8<R25>, DwarfRegNum<25>;
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def X26 : GP8<R26>, DwarfRegNum<26>;
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def X27 : GP8<R27>, DwarfRegNum<27>;
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def X28 : GP8<R28>, DwarfRegNum<28>;
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def X29 : GP8<R29>, DwarfRegNum<29>;
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def X30 : GP8<R30>, DwarfRegNum<30>;
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def X31 : GP8<R31>, DwarfRegNum<31>;
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// Floating-point registers
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def F0 : FPR< 0, "f0">, DwarfRegNum<32>;
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def F1 : FPR< 1, "f1">, DwarfRegNum<33>;
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def F2 : FPR< 2, "f2">, DwarfRegNum<34>;
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def F3 : FPR< 3, "f3">, DwarfRegNum<35>;
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def F4 : FPR< 4, "f4">, DwarfRegNum<36>;
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def F5 : FPR< 5, "f5">, DwarfRegNum<37>;
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def F6 : FPR< 6, "f6">, DwarfRegNum<38>;
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def F7 : FPR< 7, "f7">, DwarfRegNum<39>;
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def F8 : FPR< 8, "f8">, DwarfRegNum<40>;
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def F9 : FPR< 9, "f9">, DwarfRegNum<41>;
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def F10 : FPR<10, "f10">, DwarfRegNum<42>;
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def F11 : FPR<11, "f11">, DwarfRegNum<43>;
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def F12 : FPR<12, "f12">, DwarfRegNum<44>;
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def F13 : FPR<13, "f13">, DwarfRegNum<45>;
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def F14 : FPR<14, "f14">, DwarfRegNum<46>;
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def F15 : FPR<15, "f15">, DwarfRegNum<47>;
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def F16 : FPR<16, "f16">, DwarfRegNum<48>;
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def F17 : FPR<17, "f17">, DwarfRegNum<49>;
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def F18 : FPR<18, "f18">, DwarfRegNum<50>;
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def F19 : FPR<19, "f19">, DwarfRegNum<51>;
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def F20 : FPR<20, "f20">, DwarfRegNum<52>;
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def F21 : FPR<21, "f21">, DwarfRegNum<53>;
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def F22 : FPR<22, "f22">, DwarfRegNum<54>;
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def F23 : FPR<23, "f23">, DwarfRegNum<55>;
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def F24 : FPR<24, "f24">, DwarfRegNum<56>;
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def F25 : FPR<25, "f25">, DwarfRegNum<57>;
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def F26 : FPR<26, "f26">, DwarfRegNum<58>;
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def F27 : FPR<27, "f27">, DwarfRegNum<59>;
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def F28 : FPR<28, "f28">, DwarfRegNum<60>;
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def F29 : FPR<29, "f29">, DwarfRegNum<61>;
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def F30 : FPR<30, "f30">, DwarfRegNum<62>;
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def F31 : FPR<31, "f31">, DwarfRegNum<63>;
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// Vector registers
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def V0 : VR< 0, "v0">, DwarfRegNum<77>;
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def V1 : VR< 1, "v1">, DwarfRegNum<78>;
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def V2 : VR< 2, "v2">, DwarfRegNum<79>;
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def V3 : VR< 3, "v3">, DwarfRegNum<80>;
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def V4 : VR< 4, "v4">, DwarfRegNum<81>;
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def V5 : VR< 5, "v5">, DwarfRegNum<82>;
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def V6 : VR< 6, "v6">, DwarfRegNum<83>;
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def V7 : VR< 7, "v7">, DwarfRegNum<84>;
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def V8 : VR< 8, "v8">, DwarfRegNum<85>;
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def V9 : VR< 9, "v9">, DwarfRegNum<86>;
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def V10 : VR<10, "v10">, DwarfRegNum<87>;
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def V11 : VR<11, "v11">, DwarfRegNum<88>;
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def V12 : VR<12, "v12">, DwarfRegNum<89>;
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def V13 : VR<13, "v13">, DwarfRegNum<90>;
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def V14 : VR<14, "v14">, DwarfRegNum<91>;
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def V15 : VR<15, "v15">, DwarfRegNum<92>;
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def V16 : VR<16, "v16">, DwarfRegNum<93>;
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def V17 : VR<17, "v17">, DwarfRegNum<94>;
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def V18 : VR<18, "v18">, DwarfRegNum<95>;
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def V19 : VR<19, "v19">, DwarfRegNum<96>;
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def V20 : VR<20, "v20">, DwarfRegNum<97>;
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def V21 : VR<21, "v21">, DwarfRegNum<98>;
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def V22 : VR<22, "v22">, DwarfRegNum<99>;
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def V23 : VR<23, "v23">, DwarfRegNum<100>;
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def V24 : VR<24, "v24">, DwarfRegNum<101>;
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def V25 : VR<25, "v25">, DwarfRegNum<102>;
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def V26 : VR<26, "v26">, DwarfRegNum<103>;
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def V27 : VR<27, "v27">, DwarfRegNum<104>;
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def V28 : VR<28, "v28">, DwarfRegNum<105>;
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def V29 : VR<29, "v29">, DwarfRegNum<106>;
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def V30 : VR<30, "v30">, DwarfRegNum<107>;
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def V31 : VR<31, "v31">, DwarfRegNum<108>;
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// Condition registers
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def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
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def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
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def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
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def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
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def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
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def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
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def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
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def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
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// Link register
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def LR : SPR<8, "lr">, DwarfRegNum<65>;
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//let Aliases = [LR] in
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def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
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// Count register
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def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
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def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
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// VRsave register
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def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
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/// Register classes
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// Allocate volatiles first
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// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
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def GPRC : RegisterClass<"PPC", [i32], 32,
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[R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
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R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R2, R13, R31, R0, R1, LR]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRCClass::iterator
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GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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GPRCClass::iterator
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GPRCClass::allocation_order_end(const MachineFunction &MF) const {
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// In Linux, r2 is reserved for the OS.
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if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
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return end()-6;
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// On PPC64, r13 is the thread pointer. Never allocate this register.
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// Note that this is overconservative, as it also prevents allocation of
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// R31 when the FP is not needed.
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if (MF.getTarget().getSubtarget<PPCSubtarget>().isPPC64())
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return end()-5; // don't allocate R13, R31, R0, R1, LR
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if (needsFP(MF))
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return end()-4; // don't allocate R31, R0, R1, LR
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else
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return end()-3; // don't allocate R0, R1, LR
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}
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}];
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}
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def G8RC : RegisterClass<"PPC", [i64], 64,
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[X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
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X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
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X16, X15, X14, X31, X13, X0, X1, LR8]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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G8RCClass::iterator
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G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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G8RCClass::iterator
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G8RCClass::allocation_order_end(const MachineFunction &MF) const {
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if (needsFP(MF))
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return end()-5;
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else
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return end()-4;
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}
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}];
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}
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def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
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[V2, V3, V4, V5, V0, V1,
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V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
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V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
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def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
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CR3, CR4]>;
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