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https://github.com/c64scene-ar/llvm-6502.git
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a98a486ad1
load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.8 KiB
C++
87 lines
2.8 KiB
C++
//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSREGISTERINFO_H
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#define MIPSREGISTERINFO_H
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#include "Mips.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "MipsGenRegisterInfo.inc"
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namespace llvm {
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class MipsSubtarget;
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class Type;
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class MipsRegisterInfo : public MipsGenRegisterInfo {
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protected:
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const MipsSubtarget &Subtarget;
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public:
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MipsRegisterInfo(const MipsSubtarget &Subtarget);
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Get PIC indirect call register
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static unsigned getPICCallReg();
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/// Adjust the Mips stack frame.
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void adjustMipsStackFrame(MachineFunction &MF) const;
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/// Code Generation virtual methods...
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const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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static const uint32_t *getMips16RetHelperMask();
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BitVector getReservedRegs(const MachineFunction &MF) const;
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
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virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
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/// Stack Frame Processing Methods
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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/// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const;
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/// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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/// \brief Return GPR register class.
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virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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private:
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virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
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int FrameIndex, uint64_t StackSize,
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int64_t SPOffset) const = 0;
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};
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} // end namespace llvm
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#endif
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