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3e5734dc38
The ARM ARM states that CPSR may not be updated by a MUL in thumb mode. Due to an ordering of Thumb 2 Size Reduction and If Conversion, we would end up generating a THUMB MULS inside an IT block. The If Conversion pass uses the TTI isPredicable method to ensure that it can transform a Basic Block. However, because we only check for IT handling on Thumb2 functions, we may miss some cases. Even then, it only validates that the CPSR is not *live* rather than it is not accessed. This corrects the handling for that particular case since the same restriction does not hold on the vast majority of the instructions. This does prevent the IfConversion optimization from kicking in in certain cases, but generating correct code is more valuable. Addresses PR20555. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215328 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
666 B
LLVM
26 lines
666 B
LLVM
; RUN: llc -mtriple thumbv7-eabi -arm-restrict-it -filetype asm -o - %s \
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; RUN: | FileCheck %s
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define arm_aapcscc i32 @function(i32 %i, i32 %j) {
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entry:
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%cmp = icmp eq i32 %i, %j
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%mul = mul nsw i32 %i, %i
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%i.addr.0 = phi i32 [ %mul, %if.then ], [ %i, %entry ]
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ret i32 %i.addr.0
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}
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; CHECK-LABEL: function
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; CHECK: cmp r0, r1
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; CHECK: bne [[LABEL:[.*]]]
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; CHECK-NOT: mulseq r0, r0, r0
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; CHECK: [[LABEL]]
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; CHECK: muls r0, r0, r0
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; CHECK: bx lr
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