llvm-6502/test/CodeGen/ARM/frame-register.ll
Saleem Abdulrasool bf3e78f572 ARM: improve WoA ABI conformance for frame register
Windows on ARM uses R11 for the frame pointer even though the environment is a
pure Thumb-2, thumb-only environment.  Replicate this behaviour to improve
Windows ABI compatibility.  This register is used for fast stack walking, and
thus is part of the Windows ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-18 04:12:52 +00:00

39 lines
1.1 KiB
LLVM

; RUN: llc -mtriple arm-eabi -disable-fp-elim -filetype asm -o - %s \
; RUN: | FileCheck -check-prefix CHECK-ARM %s
; RUN: llc -mtriple thumb-eabi -disable-fp-elim -filetype asm -o - %s \
; RUN: | FileCheck -check-prefix CHECK-THUMB %s
; RUN: llc -mtriple arm-darwin -disable-fp-elim -filetype asm -o - %s \
; RUN: | FileCheck -check-prefix CHECK-DARWIN-ARM %s
; RUN: llc -mtriple thumb-darwin -disable-fp-elim -filetype asm -o - %s \
; RUN: | FileCheck -check-prefix CHECK-DARWIN-THUMB %s
declare void @callee(i32)
define i32 @calleer(i32 %i) {
entry:
%i.addr = alloca i32, align 4
%j = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4
%0 = load i32* %i.addr, align 4
%add = add nsw i32 %0, 1
store i32 %add, i32* %j, align 4
%1 = load i32* %j, align 4
call void @callee(i32 %1)
%2 = load i32* %j, align 4
%add1 = add nsw i32 %2, 1
ret i32 %add1
}
; CHECK-ARM: push {r11, lr}
; CHECK-ARM: mov r11, sp
; CHECK-THUMB: push {r4, r6, r7, lr}
; CHECK-THUMB: add r7, sp, #8
; CHECK-DARWIN-ARM: push {r7, lr}
; CHECK-DARWIN-THUMB: push {r4, r7, lr}