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https://github.com/c64scene-ar/llvm-6502.git
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5211134fbd
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.7 KiB
LLVM
49 lines
1.7 KiB
LLVM
; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS
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; Radar 10266272
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios4.0.0"
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; STATS-NOT: machine-sink
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define i32 @foo(i32 %h) nounwind readonly ssp {
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entry:
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%cmp = icmp slt i32 0, %h
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br i1 %cmp, label %for.body, label %if.end299
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for.body: ; preds = %for.cond
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%v.5 = select i1 undef, i32 undef, i32 0
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%0 = load i8* undef, align 1, !tbaa !0
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%conv88 = zext i8 %0 to i32
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%sub89 = sub nsw i32 0, %conv88
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%v.8 = select i1 undef, i32 undef, i32 %sub89
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%1 = load i8* null, align 1, !tbaa !0
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%conv108 = zext i8 %1 to i32
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%2 = load i8* undef, align 1, !tbaa !0
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%conv110 = zext i8 %2 to i32
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%sub111 = sub nsw i32 %conv108, %conv110
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%cmp112 = icmp slt i32 %sub111, 0
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%sub115 = sub nsw i32 0, %sub111
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%v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111
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%add62 = add i32 0, %v.5
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%add73 = add i32 %add62, 0
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%add84 = add i32 %add73, 0
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%add95 = add i32 %add84, %v.8
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%add106 = add i32 %add95, 0
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%add117 = add i32 %add106, %v.10
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%add128 = add i32 %add117, 0
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%add139 = add i32 %add128, 0
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%add150 = add i32 %add139, 0
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%add161 = add i32 %add150, 0
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%add172 = add i32 %add161, 0
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br i1 undef, label %for.cond, label %if.end299
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if.end299: ; preds = %for.body, %for.cond
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%s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ]
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ret i32 %s.10
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}
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!0 = metadata !{metadata !"omnipotent char", metadata !1}
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!1 = metadata !{metadata !"Simple C/C++ TBAA", null}
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