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https://github.com/c64scene-ar/llvm-6502.git
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00e08fcaa0
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.3 KiB
C++
95 lines
3.3 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIRegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
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#define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
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#include "AMDGPURegisterInfo.h"
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namespace llvm {
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struct SIRegisterInfo : public AMDGPURegisterInfo {
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SIRegisterInfo(const AMDGPUSubtarget &st);
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const override;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
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unsigned getHWRegIndex(unsigned Reg) const override;
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/// \brief Return the 'base' register class for this register.
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/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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/// \returns true if this class contains only SGPR registers
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bool isSGPRClass(const TargetRegisterClass *RC) const;
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/// \returns true if this class contains VGPR registers.
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bool hasVGPRs(const TargetRegisterClass *RC) const;
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/// \returns A VGPR reg class with the same width as \p SRC
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const TargetRegisterClass *getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const;
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/// \returns The register class that is used for a sub-register of \p RC for
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/// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
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/// be returned.
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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/// \p Channel This is the register channel (e.g. a value from 0-16), not the
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/// SubReg index.
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/// \returns The sub-register of Reg that is in Channel.
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unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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unsigned Channel) const;
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/// \returns True if operands defined with this register class can accept
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/// inline immediates.
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bool regClassCanUseImmediate(int RCID) const;
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/// \returns True if operands defined with this register class can accept
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/// inline immediates.
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bool regClassCanUseImmediate(const TargetRegisterClass *RC) const;
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enum PreloadedValue {
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TGID_X,
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TGID_Y,
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TGID_Z,
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SCRATCH_WAVE_OFFSET,
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SCRATCH_PTR
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};
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/// \brief Returns the physical register that \p Value is stored in.
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unsigned getPreloadedValue(const MachineFunction &MF,
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enum PreloadedValue Value) const;
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};
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} // End namespace llvm
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#endif
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