mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 02:33:33 +00:00
a25f933396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115061 91177308-0d34-0410-b5e6-96231b3b80d8
477 lines
10 KiB
ArmAsm
477 lines
10 KiB
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s > %t 2> %t.err
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// RUN: FileCheck < %t %s
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// RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
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// CHECK: subb %al, %al
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subb %al, %al
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// CHECK: addl $24, %eax
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addl $24, %eax
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// CHECK: movl %eax, 10(%ebp)
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movl %eax, 10(%ebp)
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// CHECK: movl %eax, 10(%ebp,%ebx)
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movl %eax, 10(%ebp, %ebx)
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// CHECK: movl %eax, 10(%ebp,%ebx,4)
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movl %eax, 10(%ebp, %ebx, 4)
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// CHECK: movl %eax, 10(,%ebx,4)
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movl %eax, 10(, %ebx, 4)
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// CHECK: movl 0, %eax
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movl 0, %eax
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// CHECK: movl $0, %eax
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movl $0, %eax
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// CHECK: ret
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ret
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// FIXME: Check that this matches SUB32ri8
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// CHECK: subl $1, %eax
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subl $1, %eax
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// FIXME: Check that this matches SUB32ri8
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// CHECK: subl $-1, %eax
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subl $-1, %eax
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// FIXME: Check that this matches SUB32ri
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// CHECK: subl $256, %eax
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subl $256, %eax
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// FIXME: Check that this matches XOR64ri8
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// CHECK: xorq $1, %rax
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xorq $1, %rax
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// FIXME: Check that this matches XOR64ri32
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// CHECK: xorq $256, %rax
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xorq $256, %rax
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// FIXME: Check that this matches SUB8rr
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// CHECK: subb %al, %bl
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subb %al, %bl
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// FIXME: Check that this matches SUB16rr
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// CHECK: subw %ax, %bx
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subw %ax, %bx
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// FIXME: Check that this matches SUB32rr
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// CHECK: subl %eax, %ebx
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subl %eax, %ebx
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// FIXME: Check that this matches the correct instruction.
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// CHECK: callq *%rax
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call *%rax
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// FIXME: Check that this matches the correct instruction.
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// CHECK: shldl %cl, %eax, %ebx
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shldl %cl, %eax, %ebx
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// CHECK: shll $2, %eax
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shll $2, %eax
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// CHECK: shll $2, %eax
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sall $2, %eax
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// CHECK: rep
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// CHECK: insb
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rep;insb
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// CHECK: rep
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// CHECK: outsb
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rep;outsb
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// CHECK: rep
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// CHECK: movsb
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rep;movsb
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// rdar://8470918
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smovb // CHECK: movsb
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smovw // CHECK: movsw
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smovl // CHECK: movsl
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smovq // CHECK: movsq
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// rdar://8456361
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// CHECK: rep
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// CHECK: movsl
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rep movsd
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// CHECK: rep
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// CHECK: lodsb
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rep;lodsb
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// CHECK: rep
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// CHECK: stosb
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rep;stosb
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// NOTE: repz and repe have the same opcode as rep
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// CHECK: rep
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// CHECK: cmpsb
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repz;cmpsb
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// NOTE: repnz has the same opcode as repne
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// CHECK: repne
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// CHECK: cmpsb
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repnz;cmpsb
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// NOTE: repe and repz have the same opcode as rep
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// CHECK: rep
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// CHECK: scasb
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repe;scasb
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// CHECK: repne
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// CHECK: scasb
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repne;scasb
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// CHECK: lock
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// CHECK: cmpxchgb %al, (%ebx)
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lock;cmpxchgb %al, 0(%ebx)
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// CHECK: cs
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// CHECK: movb (%eax), %al
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cs;movb 0(%eax), %al
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// CHECK: ss
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// CHECK: movb (%eax), %al
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ss;movb 0(%eax), %al
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// CHECK: ds
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// CHECK: movb (%eax), %al
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ds;movb 0(%eax), %al
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// CHECK: es
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// CHECK: movb (%eax), %al
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es;movb 0(%eax), %al
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// CHECK: fs
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// CHECK: movb (%eax), %al
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fs;movb 0(%eax), %al
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// CHECK: gs
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// CHECK: movb (%eax), %al
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gs;movb 0(%eax), %al
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// CHECK: fadd %st(0)
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// CHECK: fadd %st(1)
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// CHECK: fadd %st(7)
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fadd %st(0)
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fadd %st(1)
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fadd %st(7)
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// CHECK: leal 0, %eax
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leal 0, %eax
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// rdar://7986634 - Insensitivity on opcodes.
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// CHECK: int3
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INT3
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// Allow scale factor without index register.
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// CHECK: movaps %xmm3, (%esi)
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// CHECK-STDERR: warning: scale factor without index register is ignored
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movaps %xmm3, (%esi, 2)
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// CHECK: imull $12, %eax, %eax
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imul $12, %eax
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// CHECK: imull %ecx, %eax
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imull %ecx, %eax
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// rdar://8208481
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// CHECK: outb %al, $161
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outb %al, $161
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// CHECK: outw %ax, $128
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outw %ax, $128
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// CHECK: inb $161, %al
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inb $161, %al
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// rdar://8017621
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// CHECK: pushq $1
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push $1
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// rdar://8017530
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// CHECK: sldtw 4
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sldt 4
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// rdar://8208499
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// CHECK: cmovnew %bx, %ax
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cmovnz %bx, %ax
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// CHECK: cmovneq %rbx, %rax
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cmovnzq %rbx, %rax
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// rdar://8407928
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// CHECK: inb $127, %al
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// CHECK: inw %dx, %ax
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// CHECK: outb %al, $127
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// CHECK: outw %ax, %dx
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// CHECK: inl %dx, %eax
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inb $0x7f
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inw %dx
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outb $0x7f
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outw %dx
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inl %dx
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// PR8114
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// CHECK: outb %al, %dx
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// CHECK: outw %ax, %dx
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// CHECK: outl %eax, %dx
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out %al, (%dx)
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out %ax, (%dx)
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outl %eax, (%dx)
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// rdar://8431422
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// CHECK: fxch %st(1)
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// CHECK: fucom %st(1)
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// CHECK: fucomp %st(1)
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// CHECK: faddp %st(1)
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// CHECK: faddp %st(0)
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// CHECK: fsubp %st(1)
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// CHECK: fsubrp %st(1)
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// CHECK: fmulp %st(1)
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// CHECK: fdivp %st(1)
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// CHECK: fdivrp %st(1)
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fxch
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fucom
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fucomp
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faddp
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faddp %st
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fsubp
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fsubrp
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fmulp
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fdivp
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fdivrp
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// CHECK: fcomi %st(1), %st(0)
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// CHECK: fcomi %st(2), %st(0)
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// CHECK: fucomi %st(1), %st(0)
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// CHECK: fucomi %st(2), %st(0)
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// CHECK: fucomi %st(2), %st(0)
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fcomi
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fcomi %st(2)
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fucomi
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fucomi %st(2)
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fucomi %st(2), %st
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// CHECK: fnstsw %ax
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// CHECK: fnstsw %ax
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// CHECK: fnstsw %ax
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// CHECK: fnstsw %ax
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fnstsw
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fnstsw %ax
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fnstsw %eax
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fnstsw %al
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// rdar://8431880
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// CHECK: rclb $1, %bl
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// CHECK: rcll $1, 3735928559(%ebx,%ecx,8)
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// CHECK: rcrl $1, %ecx
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// CHECK: rcrl $1, 305419896
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rcl %bl
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rcll 0xdeadbeef(%ebx,%ecx,8)
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rcr %ecx
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rcrl 0x12345678
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// rdar://8418316
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// CHECK: shldw $1, %bx, %bx
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// CHECK: shldw $1, %bx, %bx
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// CHECK: shrdw $1, %bx, %bx
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// CHECK: shrdw $1, %bx, %bx
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shld %bx,%bx
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shld $1, %bx,%bx
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shrd %bx,%bx
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shrd $1, %bx,%bx
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// CHECK: sldtl %ecx
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// CHECK: encoding: [0x0f,0x00,0xc1]
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// CHECK: sldtw %cx
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// CHECK: encoding: [0x66,0x0f,0x00,0xc1]
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sldt %ecx
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sldt %cx
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// CHECK: lcalll *3135175374
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// CHECK: ljmpl *3135175374
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lcall *0xbadeface
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ljmp *0xbadeface
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// rdar://8444631
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// CHECK: enter $31438, $0
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// CHECK: encoding: [0xc8,0xce,0x7a,0x00]
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// CHECK: enter $31438, $1
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// CHECK: encoding: [0xc8,0xce,0x7a,0x01]
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// CHECK: enter $31438, $127
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// CHECK: encoding: [0xc8,0xce,0x7a,0x7f]
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enter $0x7ace,$0
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enter $0x7ace,$1
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enter $0x7ace,$0x7f
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// rdar://8456389
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// CHECK: fstps (%eax)
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// CHECK: encoding: [0x67,0xd9,0x18]
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fstp (%eax)
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// rdar://8456364
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// CHECK: movw %cs, %ax
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mov %CS, %ax
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// rdar://8456391
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fcmovb %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
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fcmove %st(1), %st(0) // CHECK: fcmove %st(1), %st(0)
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fcmovbe %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
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fcmovu %st(1), %st(0) // CHECK: fcmovu %st(1), %st(0)
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fcmovnb %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
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fcmovne %st(1), %st(0) // CHECK: fcmovne %st(1), %st(0)
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fcmovnbe %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
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fcmovnu %st(1), %st(0) // CHECK: fcmovnu %st(1), %st(0)
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fcmovnae %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
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fcmovna %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
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fcmovae %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
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fcmova %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
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// rdar://8456417
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.byte 88 + 1 & 15 // CHECK: .byte 9
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// rdar://8456412
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mov %rdx, %cr0
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// CHECK: movq %rdx, %cr0
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// CHECK: encoding: [0x0f,0x22,0xc2]
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mov %rdx, %cr4
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// CHECK: movq %rdx, %cr4
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// CHECK: encoding: [0x0f,0x22,0xe2]
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mov %rdx, %cr8
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// CHECK: movq %rdx, %cr8
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// CHECK: encoding: [0x44,0x0f,0x22,0xc2]
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mov %rdx, %cr15
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// CHECK: movq %rdx, %cr15
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// CHECK: encoding: [0x44,0x0f,0x22,0xfa]
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// rdar://8456371 - Handle commutable instructions written backward.
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// CHECK: faddp %st(1)
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// CHECK: fmulp %st(2)
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faddp %st, %st(1)
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fmulp %st, %st(2)
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// rdar://8468087 - Encode these accurately, they are not synonyms.
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// CHECK: fmul %st(0), %st(1)
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// CHECK: encoding: [0xdc,0xc9]
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// CHECK: fmul %st(1)
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// CHECK: encoding: [0xd8,0xc9]
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fmul %st, %st(1)
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fmul %st(1), %st
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// CHECK: fadd %st(0), %st(1)
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// CHECK: encoding: [0xdc,0xc1]
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// CHECK: fadd %st(1)
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// CHECK: encoding: [0xd8,0xc1]
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fadd %st, %st(1)
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fadd %st(1), %st
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// rdar://8416805
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// CHECK: xorb %al, %al
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// CHECK: encoding: [0x30,0xc0]
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// CHECK: xorw %di, %di
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// CHECK: encoding: [0x66,0x31,0xff]
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// CHECK: xorl %esi, %esi
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// CHECK: encoding: [0x31,0xf6]
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// CHECK: xorq %rsi, %rsi
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// CHECK: encoding: [0x48,0x31,0xf6]
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clrb %al
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clr %di
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clr %esi
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clr %rsi
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// rdar://8456378
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cltq // CHECK: cltq
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cdqe // CHECK: cltq
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cwde // CHECK: cwtl
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cwtl // CHECK: cwtl
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// rdar://8416805
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cbw // CHECK: cbtw
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cwd // CHECK: cwtd
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cdq // CHECK: cltd
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// rdar://8456378 and PR7557 - fstsw
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fstsw %ax
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// CHECK: wait
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// CHECK: fnstsw %ax
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fstsw (%rax)
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// CHECK: wait
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// CHECK: fnstsw (%rax)
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// rdar://8456382 - cvtsd2si support.
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cvtsd2si %xmm1, %rax
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// CHECK: cvtsd2siq %xmm1, %rax
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// CHECK: encoding: [0xf2,0x48,0x0f,0x2d,0xc1]
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cvtsd2si %xmm1, %eax
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// CHECK: cvtsd2sil %xmm1, %eax
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// CHECK: encoding: [0xf2,0x0f,0x2d,0xc1]
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cvtsd2siq %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
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cvtsd2sil %xmm0, %eax // CHECK: cvtsd2sil %xmm0, %eax
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cvtsd2si %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
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cvttpd2dq %xmm1, %xmm0 // CHECK: cvttpd2dq %xmm1, %xmm0
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cvttpd2dq (%rax), %xmm0 // CHECK: cvttpd2dq (%rax), %xmm0
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cvttps2dq %xmm1, %xmm0 // CHECK: cvttps2dq %xmm1, %xmm0
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cvttps2dq (%rax), %xmm0 // CHECK: cvttps2dq (%rax), %xmm0
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// rdar://8456376 - llvm-mc rejects 'roundss'
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roundss $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0a,0xc0,0x0e]
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roundps $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x08,0xc0,0x0e]
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roundsd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0b,0xc0,0x0e]
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roundpd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x09,0xc0,0x0e]
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// rdar://8482675 - 32-bit mem operand support in 64-bit mode (0x67 prefix)
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leal 8(%eax), %esi
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// CHECK: leal 8(%eax), %esi
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// CHECK: encoding: [0x67,0x8d,0x70,0x08]
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leaq 8(%eax), %rsi
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// CHECK: leaq 8(%eax), %rsi
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// CHECK: encoding: [0x67,0x48,0x8d,0x70,0x08]
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leaq 8(%rax), %rsi
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// CHECK: leaq 8(%rax), %rsi
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// CHECK: encoding: [0x48,0x8d,0x70,0x08]
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cvttpd2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5
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// CHECK: cvttpd2dq 3735928559(%ebx,%ecx,8), %xmm5
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// CHECK: encoding: [0x67,0x66,0x0f,0xe6,0xac,0xcb,0xef,0xbe,0xad,0xde]
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// rdar://8490728 - llvm-mc rejects 'movmskpd'
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movmskpd %xmm6, %rax
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// CHECK: movmskpd %xmm6, %rax
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// CHECK: encoding: [0x66,0x48,0x0f,0x50,0xc6]
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movmskpd %xmm6, %eax
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// CHECK: movmskpd %xmm6, %eax
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// CHECK: encoding: [0x66,0x0f,0x50,0xc6]
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// rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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fdivrp %st(0), %st(1) // CHECK: encoding: [0xde,0xf9]
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fdivrp %st(1), %st(0) // CHECK: encoding: [0xde,0xf9]
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fsubrp %ST(0), %ST(1) // CHECK: encoding: [0xde,0xe9]
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fsubrp %ST(1), %ST(0) // CHECK: encoding: [0xde,0xe9]
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