mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-24 06:30:19 +00:00
5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
|
; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
|
|
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
|
|
; REQUIRES: asserts
|
|
|
|
; CHECK-SSA-LABEL: Machine code for function t1
|
|
|
|
; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
|
|
; CHECK-SSA-NOT: [[QUOTREG]]<def> =
|
|
; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
|
|
|
|
; CHECK-SSA-LABEL: Machine code for function t2
|
|
|
|
define i32 @t1(i32 %a, i32 %b) {
|
|
; CHECK: @t1
|
|
; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
|
|
; CHECK: msub w0, [[TMP]], w1, w0
|
|
%1 = srem i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i64 @t2(i64 %a, i64 %b) {
|
|
; CHECK: @t2
|
|
; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
|
|
; CHECK: msub x0, [[TMP]], x1, x0
|
|
%1 = srem i64 %a, %b
|
|
ret i64 %1
|
|
}
|
|
|
|
define i32 @t3(i32 %a, i32 %b) {
|
|
; CHECK: @t3
|
|
; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
|
|
; CHECK: msub w0, [[TMP]], w1, w0
|
|
%1 = urem i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i64 @t4(i64 %a, i64 %b) {
|
|
; CHECK: @t4
|
|
; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
|
|
; CHECK: msub x0, [[TMP]], x1, x0
|
|
%1 = urem i64 %a, %b
|
|
ret i64 %1
|
|
}
|