mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-05 01:30:18 +00:00
3e99b715d1
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.3 KiB
LLVM
57 lines
1.3 KiB
LLVM
; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
|
|
|
|
define i64 @test1(i32 %xx, i32 %test) nounwind {
|
|
%conv = zext i32 %xx to i64
|
|
%and = and i32 %test, 7
|
|
%sh_prom = zext i32 %and to i64
|
|
%shl = shl i64 %conv, %sh_prom
|
|
ret i64 %shl
|
|
; CHECK: test1:
|
|
; CHECK: shll %cl, %eax
|
|
; CHECK: shrl %edx
|
|
; CHECK: xorb $31
|
|
; CHECK: shrl %cl, %edx
|
|
}
|
|
|
|
define i64 @test2(i64 %xx, i32 %test) nounwind {
|
|
%and = and i32 %test, 7
|
|
%sh_prom = zext i32 %and to i64
|
|
%shl = shl i64 %xx, %sh_prom
|
|
ret i64 %shl
|
|
; CHECK: test2:
|
|
; CHECK: shll %cl, %esi
|
|
; CHECK: shrl %edx
|
|
; CHECK: xorb $31
|
|
; CHECK: shrl %cl, %edx
|
|
; CHECK: orl %esi, %edx
|
|
; CHECK: shll %cl, %eax
|
|
}
|
|
|
|
define i64 @test3(i64 %xx, i32 %test) nounwind {
|
|
%and = and i32 %test, 7
|
|
%sh_prom = zext i32 %and to i64
|
|
%shr = lshr i64 %xx, %sh_prom
|
|
ret i64 %shr
|
|
; CHECK: test3:
|
|
; CHECK: shrl %cl, %esi
|
|
; CHECK: leal (%edx,%edx), %eax
|
|
; CHECK: xorb $31, %cl
|
|
; CHECK: shll %cl, %eax
|
|
; CHECK: orl %esi, %eax
|
|
; CHECK: shrl %cl, %edx
|
|
}
|
|
|
|
define i64 @test4(i64 %xx, i32 %test) nounwind {
|
|
%and = and i32 %test, 7
|
|
%sh_prom = zext i32 %and to i64
|
|
%shr = ashr i64 %xx, %sh_prom
|
|
ret i64 %shr
|
|
; CHECK: test4:
|
|
; CHECK: shrl %cl, %esi
|
|
; CHECK: leal (%edx,%edx), %eax
|
|
; CHECK: xorb $31, %cl
|
|
; CHECK: shll %cl, %eax
|
|
; CHECK: orl %esi, %eax
|
|
; CHECK: sarl %cl, %edx
|
|
}
|