mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fc05f402ea
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it. This should not change generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
298 lines
8.9 KiB
C++
298 lines
8.9 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Nate Begeman and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "X86Subtarget.h"
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#include "X86GenSubtarget.inc"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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cl::opt<X86Subtarget::AsmWriterFlavorTy>
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AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumValN(X86Subtarget::ATT, "att", " Emit AT&T-style assembly"),
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clEnumValN(X86Subtarget::Intel, "intel", " Emit Intel-style assembly"),
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clEnumValEnd));
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/// True if accessing the GV requires an extra load. For Windows, dllimported
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/// symbols are indirect, loading the value at address GV rather then the
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/// value of GV itself. This means that the GlobalAddress must be in the base
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/// or index register of the address, not the GV offset field.
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bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
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const TargetMachine& TM,
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bool isDirectCall) const
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{
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// FIXME: PIC
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if (TM.getRelocationModel() != Reloc::Static)
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if (isTargetDarwin()) {
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return (!isDirectCall &&
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(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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(GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())));
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} else if (TM.getRelocationModel() == Reloc::PIC_ && isPICStyleGOT()) {
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// Extra load is needed for all non-statics.
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return (!isDirectCall &&
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(GV->isDeclaration() || !GV->hasInternalLinkage()));
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} else if (isTargetCygMing() || isTargetWindows()) {
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return (GV->hasDLLImportLinkage());
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}
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return false;
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#endif
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#endif
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return true;
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
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return;
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X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
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if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
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if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
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if (ECX & 0x1) X86SSELevel = SSE3;
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if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
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if (memcmp(text.c, "GenuineIntel", 12) == 0 ||
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memcmp(text.c, "AuthenticAMD", 12) == 0) {
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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HasX86_64 = (EDX >> 29) & 0x1;
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}
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}
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static const char *GetCurrentX86CPU() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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unsigned Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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union {
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unsigned u[3];
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char c[12];
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} text;
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X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 4: return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: return "pentiumpro";
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case 3:
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case 5:
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case 6: return "pentium2";
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case 7:
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case 8:
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case 10:
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case 11: return "pentium3";
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15: return "core2";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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return (Em64T) ? "nocona" : "prescott";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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switch (Model) {
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case 1: return "opteron";
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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default:
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return "generic";
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}
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} else {
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return "generic";
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}
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}
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X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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: AsmFlavor(AsmWriterFlavor)
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, PICStyle(PICStyle::None)
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, X86SSELevel(NoMMXSSE)
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, HasX86_64(false)
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, stackAlignment(8)
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// FIXME: this is a known good value for Yonah. How about others?
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, MaxInlineSizeThreshold(128)
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, Is64Bit(is64Bit)
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, HasLow4GUserAddress(true)
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, TargetType(isELF) { // Default to ELF unless otherwise specified.
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// Determine default and user specified characteristics
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if (!FS.empty()) {
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// If feature string is not empty, parse features string.
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std::string CPU = GetCurrentX86CPU();
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ParseSubtargetFeatures(FS, CPU);
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if (Is64Bit && !HasX86_64)
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cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
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<< "requested.\n";
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if (Is64Bit && X86SSELevel < SSE2)
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cerr << "Warning: 64-bit processors all have at least SSE2.\n";
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} else {
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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}
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// If requesting codegen for X86-64, make sure that 64-bit and SSE2 features
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// are enabled. These are available on all x86-64 CPUs.
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if (Is64Bit) {
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HasX86_64 = true;
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if (X86SSELevel < SSE2)
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X86SSELevel = SSE2;
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}
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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const std::string& TT = M.getTargetTriple();
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if (TT.length() > 5) {
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if (TT.find("cygwin") != std::string::npos)
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TargetType = isCygwin;
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else if (TT.find("mingw") != std::string::npos)
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TargetType = isMingw;
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else if (TT.find("darwin") != std::string::npos)
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TargetType = isDarwin;
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else if (TT.find("win32") != std::string::npos)
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TargetType = isWindows;
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} else if (TT.empty()) {
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#if defined(__CYGWIN__)
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TargetType = isCygwin;
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#elif defined(__MINGW32__)
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TargetType = isMingw;
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#elif defined(__APPLE__)
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TargetType = isDarwin;
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#elif defined(_WIN32)
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TargetType = isWindows;
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#endif
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}
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// If the asm syntax hasn't been overridden on the command line, use whatever
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// the target wants.
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if (AsmFlavor == X86Subtarget::Unset) {
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if (TargetType == isWindows) {
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AsmFlavor = X86Subtarget::Intel;
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} else {
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AsmFlavor = X86Subtarget::ATT;
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}
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}
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if (TargetType == isDarwin && Is64Bit)
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HasLow4GUserAddress = false;
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if (TargetType == isDarwin ||
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TargetType == isCygwin ||
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TargetType == isMingw ||
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(TargetType == isELF && Is64Bit))
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stackAlignment = 16;
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}
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