mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
4.7 KiB
LLVM
121 lines
4.7 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
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; rdar://7353541
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; rdar://7354376
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@GV = external global i32 ; <i32*> [#uses=2]
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define void @t1(i32* nocapture %vals, i32 %c) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: bxeq lr
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%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb.nph
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bb.nph: ; preds = %entry
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; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
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; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
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; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
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; CHECK: ldr{{.*}}, [r[[R2b]]
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; CHECK: LBB0_
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; CHECK-NOT: LCPI0_0:
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; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
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; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
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; PIC: add r[[R2]], pc
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; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
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; PIC: ldr{{.*}}, [r[[R2b]]
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; PIC: LBB0_
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; PIC-NOT: LCPI0_0:
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; PIC: .section
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%.pre = load i32, i32* @GV, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
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%i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
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%scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
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%2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
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store i32 %3, i32* @GV, align 4
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%4 = add i32 %i.03, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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; rdar://8001136
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define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: vmov.f32 q{{.*}}, #1.000000e+00
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK: %bb1
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
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%tmp1 = shl i32 %indvar, 2
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%gep1 = getelementptr i8, i8* %ptr1, i32 %tmp1
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%tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
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%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
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%gep2 = getelementptr i8, i8* %ptr2, i32 %tmp1
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call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
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%indvar.next = add i32 %indvar, 1
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%cond = icmp eq i32 %indvar.next, 10
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br i1 %cond, label %bb2, label %bb1
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bb2:
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ret void
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}
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; CHECK-NOT: LCPI1_0:
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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; rdar://8241368
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; isel should not fold immediate into eor's which would have prevented LICM.
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define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone {
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; CHECK-LABEL: t3:
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bb.nph:
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; CHECK: bb.nph
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; CHECK: movw {{(r[0-9])|(lr)}}, #32768
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; CHECK: movs {{(r[0-9]+)|(lr)}}, #0
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; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386
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; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534
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; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535
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br label %bb
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bb: ; preds = %bb, %bb.nph
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; CHECK: bb
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; CHECK: eor.w
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; CHECK: eorne.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
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; CHECK-NOT: eor
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; CHECK: and
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%data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]
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%crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; <i16> [#uses=3]
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%i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ] ; <i8> [#uses=1]
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%0 = trunc i16 %crc_addr.112 to i8 ; <i8> [#uses=1]
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%1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1]
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%2 = and i8 %1, 1 ; <i8> [#uses=1]
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%3 = icmp eq i8 %2, 0 ; <i1> [#uses=2]
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%4 = xor i16 %crc_addr.112, 16386 ; <i16> [#uses=1]
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%crc_addr.0 = select i1 %3, i16 %crc_addr.112, i16 %4 ; <i16> [#uses=1]
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%5 = lshr i16 %crc_addr.0, 1 ; <i16> [#uses=2]
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%6 = or i16 %5, -32768 ; <i16> [#uses=1]
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%crc_addr.2 = select i1 %3, i16 %5, i16 %6 ; <i16> [#uses=2]
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%7 = add i8 %i.011, 1 ; <i8> [#uses=2]
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%8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1]
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%exitcond = icmp eq i8 %7, 8 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb8, label %bb
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bb8: ; preds = %bb
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ret i16 %crc_addr.2
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}
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