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922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
6.6 KiB
TableGen
137 lines
6.6 KiB
TableGen
//=- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Intel Atom (Bonnell)
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// processors.
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//
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//===----------------------------------------------------------------------===//
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//
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// Scheduling information derived from the "Intel 64 and IA32 Architectures
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// Optimization Reference Manual", Chapter 13, Section 4.
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// Functional Units
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// Port 0
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def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
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// SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
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def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
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// SIMD/FP: SIMD ALU, FP Adder
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def AtomItineraries : ProcessorItineraries<
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[ Port0, Port1 ],
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[], [
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// P0 only
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// InstrItinData<class, [InstrStage<N, [P0]>] >,
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// P0 or P1
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// InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
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// P0 and P1
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// InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
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//
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// Default is 1 cycle, port0 or port1
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InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
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InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
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InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
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// mul
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InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
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// imul by al, ax, eax, rax
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InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
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// imul reg by reg|mem
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InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
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InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
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InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
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// imul reg = reg/mem * imm
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InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
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InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
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InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
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// idiv
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InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
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// div
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InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
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// neg/not/inc/dec
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InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
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// add/sub/and/or/xor/adc/sbc/cmp/test
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InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
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// shift/rotate
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InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
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// shift double
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InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
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InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
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// cmov
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InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
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InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
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InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
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InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
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InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
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// set
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InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
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InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
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// jcc
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InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
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// jcxz/jecxz/jrcxz
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InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
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// jmp rel
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InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
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// jmp indirect
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InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
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InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
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// jmp far
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InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
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InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
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// loop/loope/loopne
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InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
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InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
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// call - all but reg/imm
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InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
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InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
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InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
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InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
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//ret
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InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
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InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >
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]>;
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