mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-11 08:07:22 +00:00
ed18a3e6b2
This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157027 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
1.7 KiB
LLVM
86 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
|
|
|
|
; These tests could be improved by 'movs r0, #0' being rematerialized below the
|
|
; test as 'mov.w r0, #0'.
|
|
|
|
define i1 @f1(i32 %a, i32 %b) {
|
|
%nb = sub i32 0, %b
|
|
%tmp = icmp ne i32 %a, %nb
|
|
ret i1 %tmp
|
|
}
|
|
; CHECK: f1:
|
|
; CHECK: cmn {{.*}}, r1
|
|
|
|
define i1 @f2(i32 %a, i32 %b) {
|
|
%nb = sub i32 0, %b
|
|
%tmp = icmp ne i32 %nb, %a
|
|
ret i1 %tmp
|
|
}
|
|
; CHECK: f2:
|
|
; CHECK: cmn {{.*}}, r1
|
|
|
|
define i1 @f3(i32 %a, i32 %b) {
|
|
%nb = sub i32 0, %b
|
|
%tmp = icmp eq i32 %a, %nb
|
|
ret i1 %tmp
|
|
}
|
|
; CHECK: f3:
|
|
; CHECK: cmn {{.*}}, r1
|
|
|
|
define i1 @f4(i32 %a, i32 %b) {
|
|
%nb = sub i32 0, %b
|
|
%tmp = icmp eq i32 %nb, %a
|
|
ret i1 %tmp
|
|
}
|
|
; CHECK: f4:
|
|
; CHECK: cmn {{.*}}, r1
|
|
|
|
define i1 @f5(i32 %a, i32 %b) {
|
|
%tmp = shl i32 %b, 5
|
|
%nb = sub i32 0, %tmp
|
|
%tmp1 = icmp eq i32 %nb, %a
|
|
ret i1 %tmp1
|
|
}
|
|
; CHECK: f5:
|
|
; CHECK: cmn.w {{.*}}, r1, lsl #5
|
|
|
|
define i1 @f6(i32 %a, i32 %b) {
|
|
%tmp = lshr i32 %b, 6
|
|
%nb = sub i32 0, %tmp
|
|
%tmp1 = icmp ne i32 %nb, %a
|
|
ret i1 %tmp1
|
|
}
|
|
; CHECK: f6:
|
|
; CHECK: cmn.w {{.*}}, r1, lsr #6
|
|
|
|
define i1 @f7(i32 %a, i32 %b) {
|
|
%tmp = ashr i32 %b, 7
|
|
%nb = sub i32 0, %tmp
|
|
%tmp1 = icmp eq i32 %a, %nb
|
|
ret i1 %tmp1
|
|
}
|
|
; CHECK: f7:
|
|
; CHECK: cmn.w {{.*}}, r1, asr #7
|
|
|
|
define i1 @f8(i32 %a, i32 %b) {
|
|
%l8 = shl i32 %a, 24
|
|
%r8 = lshr i32 %a, 8
|
|
%tmp = or i32 %l8, %r8
|
|
%nb = sub i32 0, %tmp
|
|
%tmp1 = icmp ne i32 %a, %nb
|
|
ret i1 %tmp1
|
|
}
|
|
; CHECK: f8:
|
|
; CHECK: cmn.w {{.*}}, {{.*}}, ror #8
|
|
|
|
|
|
define void @f9(i32 %a, i32 %b) nounwind optsize {
|
|
tail call void asm sideeffect "cmn.w r0, r1", ""() nounwind, !srcloc !0
|
|
ret void
|
|
}
|
|
|
|
!0 = metadata !{i32 81}
|
|
|
|
; CHECK: f9:
|
|
; CHECK: cmn.w r0, r1
|