Andrew Trick 64925c55c6 Enable LSR IV Chains with sufficient heuristics. ... These heuristics are sufficient for enabling IV chains by default. Performance analysis has been done for i386, x86_64, and thumbv7. The optimization is rarely important, but can significantly speed up certain cases by eliminating spill code within the loop. Unrolled loops are prime candidates for IV chains. In many cases, the final code could still be improved with more target specific optimization following LSR. The goal of this feature is for LSR to make the best choice of induction variables. Instruction selection may not completely take advantage of this feature yet. As a result, there could be cases of slight code size increase. Code size can be worse on x86 because it doesn't support postincrement addressing. In fact, when chains are formed, you may see redundant address plus stride addition in the addressing mode. GenerateIVChains tries to compensate for the common cases. On ARM, code size increase can be mitigated by using postincrement addressing, but downstream codegen currently misses some opportunities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147826 91177308-0d34-0410-b5e6-96231b3b80d8		2012-01-10 01:45:08 +00:00
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Hello
InstCombine	Move assert to the right place.	2012-01-09 17:36:29 +00:00
Instrumentation
IPO
Scalar	Enable LSR IV Chains with sufficient heuristics.	2012-01-10 01:45:08 +00:00
Utils
CMakeLists.txt
LLVMBuild.txt
Makefile