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This lowers frem to a runtime libcall inside fast-isel. The test case also checks the CallLoweringInfo bug that was exposed by this change. This fixes rdar://problem/18342783. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217833 91177308-0d34-0410-b5e6-96231b3b80d8
570 lines
23 KiB
C++
570 lines
23 KiB
C++
//===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the FastISel class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/IntrinsicInst.h"
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namespace llvm {
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/// \brief This is a fast-path instruction selection class that generates poor
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/// code and doesn't support illegal types or non-trivial lowering, but runs
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/// quickly.
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class FastISel {
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public:
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struct ArgListEntry {
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Value *Val;
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Type *Ty;
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bool IsSExt : 1;
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bool IsZExt : 1;
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bool IsInReg : 1;
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bool IsSRet : 1;
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bool IsNest : 1;
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bool IsByVal : 1;
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bool IsInAlloca : 1;
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bool IsReturned : 1;
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uint16_t Alignment;
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ArgListEntry()
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: Val(nullptr), Ty(nullptr), IsSExt(false), IsZExt(false),
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IsInReg(false), IsSRet(false), IsNest(false), IsByVal(false),
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IsInAlloca(false), IsReturned(false), Alignment(0) {}
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/// \brief Set CallLoweringInfo attribute flags based on a call instruction
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/// and called function attributes.
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void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
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};
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typedef std::vector<ArgListEntry> ArgListTy;
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struct CallLoweringInfo {
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Type *RetTy;
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bool RetSExt : 1;
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bool RetZExt : 1;
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bool IsVarArg : 1;
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bool IsInReg : 1;
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bool DoesNotReturn : 1;
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bool IsReturnValueUsed : 1;
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// \brief IsTailCall Should be modified by implementations of FastLowerCall
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// that perform tail call conversions.
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bool IsTailCall;
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unsigned NumFixedArgs;
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CallingConv::ID CallConv;
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const Value *Callee;
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const char *SymName;
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ArgListTy Args;
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ImmutableCallSite *CS;
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MachineInstr *Call;
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unsigned ResultReg;
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unsigned NumResultRegs;
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SmallVector<Value *, 16> OutVals;
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SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
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SmallVector<unsigned, 16> OutRegs;
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SmallVector<ISD::InputArg, 4> Ins;
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SmallVector<unsigned, 4> InRegs;
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CallLoweringInfo()
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: RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
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IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
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IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
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Callee(nullptr), SymName(nullptr), CS(nullptr), Call(nullptr),
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ResultReg(0), NumResultRegs(0) {}
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CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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const Value *Target, ArgListTy &&ArgsList,
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ImmutableCallSite &Call) {
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RetTy = ResultTy;
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Callee = Target;
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IsInReg = Call.paramHasAttr(0, Attribute::InReg);
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DoesNotReturn = Call.doesNotReturn();
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IsVarArg = FuncTy->isVarArg();
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IsReturnValueUsed = !Call.getInstruction()->use_empty();
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RetSExt = Call.paramHasAttr(0, Attribute::SExt);
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RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
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CallConv = Call.getCallingConv();
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Args = std::move(ArgsList);
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NumFixedArgs = FuncTy->getNumParams();
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CS = &Call;
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return *this;
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}
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CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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const char *Target, ArgListTy &&ArgsList,
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ImmutableCallSite &Call,
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unsigned FixedArgs = ~0U) {
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RetTy = ResultTy;
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Callee = Call.getCalledValue();
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SymName = Target;
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IsInReg = Call.paramHasAttr(0, Attribute::InReg);
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DoesNotReturn = Call.doesNotReturn();
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IsVarArg = FuncTy->isVarArg();
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IsReturnValueUsed = !Call.getInstruction()->use_empty();
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RetSExt = Call.paramHasAttr(0, Attribute::SExt);
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RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
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CallConv = Call.getCallingConv();
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Args = std::move(ArgsList);
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NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
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CS = &Call;
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return *this;
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}
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CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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const Value *Target, ArgListTy &&ArgsList,
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unsigned FixedArgs = ~0U) {
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RetTy = ResultTy;
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Callee = Target;
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CallConv = CC;
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Args = std::move(ArgsList);
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NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
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return *this;
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}
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CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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const char *Target, ArgListTy &&ArgsList,
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unsigned FixedArgs = ~0U) {
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RetTy = ResultTy;
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SymName = Target;
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CallConv = CC;
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Args = std::move(ArgsList);
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NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
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return *this;
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}
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CallLoweringInfo &setTailCall(bool Value = true) {
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IsTailCall = Value;
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return *this;
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}
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ArgListTy &getArgs() { return Args; }
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void clearOuts() {
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OutVals.clear();
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OutFlags.clear();
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OutRegs.clear();
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}
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void clearIns() {
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Ins.clear();
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InRegs.clear();
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}
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};
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protected:
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DenseMap<const Value *, unsigned> LocalValueMap;
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FunctionLoweringInfo &FuncInfo;
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MachineFunction *MF;
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MachineRegisterInfo &MRI;
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MachineFrameInfo &MFI;
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MachineConstantPool &MCP;
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DebugLoc DbgLoc;
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const TargetMachine &TM;
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const DataLayout &DL;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const TargetRegisterInfo &TRI;
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const TargetLibraryInfo *LibInfo;
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bool SkipTargetIndependentISel;
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/// \brief The position of the last instruction for materializing constants
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/// for use in the current block. It resets to EmitStartPt when it makes sense
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/// (for example, it's usually profitable to avoid function calls between the
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/// definition and the use)
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MachineInstr *LastLocalValue;
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/// \brief The top most instruction in the current block that is allowed for
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/// emitting local variables. LastLocalValue resets to EmitStartPt when it
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/// makes sense (for example, on function calls)
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MachineInstr *EmitStartPt;
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public:
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/// \brief Return the position of the last instruction emitted for
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/// materializing constants for use in the current block.
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MachineInstr *getLastLocalValue() { return LastLocalValue; }
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/// \brief Update the position of the last instruction emitted for
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/// materializing constants for use in the current block.
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void setLastLocalValue(MachineInstr *I) {
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EmitStartPt = I;
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LastLocalValue = I;
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}
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/// \brief Set the current block to which generated machine instructions will
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/// be appended, and clear the local CSE map.
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void startNewBlock();
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/// \brief Return current debug location information.
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DebugLoc getCurDebugLoc() const { return DbgLoc; }
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/// \brief Do "fast" instruction selection for function arguments and append
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/// the machine instructions to the current block. Returns true when
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/// successful.
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bool lowerArguments();
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/// \brief Do "fast" instruction selection for the given LLVM IR instruction
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/// and append the generated machine instructions to the current block.
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/// Returns true if selection was successful.
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bool selectInstruction(const Instruction *I);
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/// \brief Do "fast" instruction selection for the given LLVM IR operator
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/// (Instruction or ConstantExpr), and append generated machine instructions
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/// to the current block. Return true if selection was successful.
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bool selectOperator(const User *I, unsigned Opcode);
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/// \brief Create a virtual register and arrange for it to be assigned the
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/// value for the given LLVM value.
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unsigned getRegForValue(const Value *V);
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/// \brief Look up the value to see if its value is already cached in a
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/// register. It may be defined by instructions across blocks or defined
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/// locally.
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unsigned lookUpRegForValue(const Value *V);
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/// \brief This is a wrapper around getRegForValue that also takes care of
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/// truncating or sign-extending the given getelementptr index value.
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std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
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/// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
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/// that we could have a sequence where multiple LLVM IR instructions are
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/// folded into the same machineinstr. For example we could have:
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///
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/// A: x = load i32 *P
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/// B: y = icmp A, 42
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/// C: br y, ...
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///
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/// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
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/// (and any other folded instructions) because it is between A and C.
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///
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/// If we succeed folding, return true.
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bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
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/// \brief The specified machine instr operand is a vreg, and that vreg is
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/// being provided by the specified load instruction. If possible, try to
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/// fold the load as an operand to the instruction, returning true if
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/// possible.
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///
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/// This method should be implemented by targets.
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virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
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const LoadInst * /*LI*/) {
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return false;
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}
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/// \brief Reset InsertPt to prepare for inserting instructions into the
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/// current block.
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void recomputeInsertPt();
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/// \brief Remove all dead instructions between the I and E.
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void removeDeadCode(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E);
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struct SavePoint {
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MachineBasicBlock::iterator InsertPt;
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DebugLoc DL;
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};
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/// \brief Prepare InsertPt to begin inserting instructions into the local
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/// value area and return the old insert position.
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SavePoint enterLocalValueArea();
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/// \brief Reset InsertPt to the given old insert position.
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void leaveLocalValueArea(SavePoint Old);
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virtual ~FastISel();
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protected:
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explicit FastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo,
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bool SkipTargetIndependentISel = false);
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/// \brief This method is called by target-independent code when the normal
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/// FastISel process fails to select an instruction. This gives targets a
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/// chance to emit code for anything that doesn't fit into FastISel's
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/// framework. It returns true if it was successful.
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virtual bool fastSelectInstruction(const Instruction *I) = 0;
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/// \brief This method is called by target-independent code to do target-
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/// specific argument lowering. It returns true if it was successful.
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virtual bool fastLowerArguments();
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/// \brief This method is called by target-independent code to do target-
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/// specific call lowering. It returns true if it was successful.
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virtual bool fastLowerCall(CallLoweringInfo &CLI);
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/// \brief This method is called by target-independent code to do target-
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/// specific intrinsic lowering. It returns true if it was successful.
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virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type and opcode be emitted.
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virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register operand be emitted.
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virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
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bool Op0IsKill);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register operands be emitted.
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virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
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bool Op0IsKill, unsigned Op1, bool Op1IsKill);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and immediate
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// operands be emitted.
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virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
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bool Op0IsKill, uint64_t Imm);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and floating-point
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/// immediate operands be emitted.
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virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
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bool Op0IsKill, const ConstantFP *FPImm);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and register and immediate
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/// operands be emitted.
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virtual unsigned fastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode,
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unsigned Op0, bool Op0IsKill, unsigned Op1,
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bool Op1IsKill, uint64_t Imm);
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/// \brief This method is a wrapper of fastEmit_ri.
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///
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/// It first tries to emit an instruction with an immediate operand using
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/// fastEmit_ri. If that fails, it materializes the immediate into a register
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/// and try fastEmit_rr instead.
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unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
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uint64_t Imm, MVT ImmType);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and immediate operand be emitted.
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virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
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/// \brief This method is called by target-independent code to request that an
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/// instruction with the given type, opcode, and floating-point immediate
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/// operand be emitted.
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virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
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const ConstantFP *FPImm);
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/// \brief Emit a MachineInstr with no operands and a result register in the
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/// given register class.
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unsigned fastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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/// \brief Emit a MachineInstr with one register operand and a result register
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/// in the given register class.
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unsigned fastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill);
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/// \brief Emit a MachineInstr with two register operands and a result
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/// register in the given register class.
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unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, unsigned Op1, bool Op1IsKill);
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/// \brief Emit a MachineInstr with three register operands and a result
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/// register in the given register class.
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unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, unsigned Op1, bool Op1IsKill,
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unsigned Op2, bool Op2IsKill);
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/// \brief Emit a MachineInstr with a register operand, an immediate, and a
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/// result register in the given register class.
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unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, uint64_t Imm);
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/// \brief Emit a MachineInstr with one register operand and two immediate
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/// operands.
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unsigned fastEmitInst_rii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
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/// \brief Emit a MachineInstr with two register operands and a result
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/// register in the given register class.
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unsigned fastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, const ConstantFP *FPImm);
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/// \brief Emit a MachineInstr with two register operands, an immediate, and a
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/// result register in the given register class.
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unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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/// \brief Emit a MachineInstr with two register operands, two immediates
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/// operands, and a result register in the given register class.
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unsigned fastEmitInst_rrii(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, unsigned Op0,
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bool Op0IsKill, unsigned Op1, bool Op1IsKill,
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uint64_t Imm1, uint64_t Imm2);
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/// \brief Emit a MachineInstr with a single immediate operand, and a result
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/// register in the given register class.
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unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC, uint64_t Imm);
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/// \brief Emit a MachineInstr with a two immediate operands.
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unsigned fastEmitInst_ii(unsigned MachineInstrOpcode,
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const TargetRegisterClass *RC, uint64_t Imm1,
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uint64_t Imm2);
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/// \brief Emit a MachineInstr for an extract_subreg from a specified index of
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/// a superregister to a specified type.
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unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
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uint32_t Idx);
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/// \brief Emit MachineInstrs to compute the value of Op with all but the
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/// least significant bit set to zero.
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unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
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/// \brief Emit an unconditional branch to the given block, unless it is the
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/// immediate (fall-through) successor, and update the CFG.
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void fastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
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/// \brief Update the value map to include the new mapping for this
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/// instruction, or insert an extra copy to get the result in a previous
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/// determined register.
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///
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/// NOTE: This is only necessary because we might select a block that uses a
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/// value before we select the block that defines the value. It might be
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/// possible to fix this by selecting blocks in reverse postorder.
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void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
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unsigned createResultReg(const TargetRegisterClass *RC);
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/// \brief Try to constrain Op so that it is usable by argument OpNum of the
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/// provided MCInstrDesc. If this fails, create a new virtual register in the
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/// correct class and COPY the value there.
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unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
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unsigned OpNum);
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/// \brief Emit a constant in a register using target-specific logic, such as
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/// constant pool loads.
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virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
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/// \brief Emit an alloca address in a register using target-specific logic.
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virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
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/// \brief Emit the floating-point constant +0.0 in a register using target-
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/// specific logic.
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virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
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return 0;
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}
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/// \brief Check if \c Add is an add that can be safely folded into \c GEP.
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///
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/// \c Add can be folded into \c GEP if:
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/// - \c Add is an add,
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/// - \c Add's size matches \c GEP's,
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/// - \c Add is in the same basic block as \c GEP, and
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/// - \c Add has a constant operand.
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bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
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/// \brief Test whether the given value has exactly one use.
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bool hasTrivialKill(const Value *V);
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/// \brief Create a machine mem operand from the given instruction.
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MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
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CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
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bool lowerCallTo(const CallInst *CI, const char *SymName, unsigned NumArgs);
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bool lowerCallTo(CallLoweringInfo &CLI);
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|
|
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bool isCommutativeIntrinsic(IntrinsicInst const *II) {
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|
switch (II->getIntrinsicID()) {
|
|
case Intrinsic::sadd_with_overflow:
|
|
case Intrinsic::uadd_with_overflow:
|
|
case Intrinsic::smul_with_overflow:
|
|
case Intrinsic::umul_with_overflow:
|
|
return true;
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|
default:
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|
return false;
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|
}
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|
}
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|
|
|
|
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bool lowerCall(const CallInst *I);
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|
/// \brief Select and emit code for a binary operator instruction, which has
|
|
/// an opcode which directly corresponds to the given ISD opcode.
|
|
bool selectBinaryOp(const User *I, unsigned ISDOpcode);
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|
bool selectFNeg(const User *I);
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|
bool selectGetElementPtr(const User *I);
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|
bool selectStackmap(const CallInst *I);
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|
bool selectPatchpoint(const CallInst *I);
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|
bool selectCall(const User *Call);
|
|
bool selectIntrinsicCall(const IntrinsicInst *II);
|
|
bool selectBitCast(const User *I);
|
|
bool selectCast(const User *I, unsigned Opcode);
|
|
bool selectExtractValue(const User *I);
|
|
bool selectInsertValue(const User *I);
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|
|
|
private:
|
|
/// \brief Handle PHI nodes in successor blocks.
|
|
///
|
|
/// Emit code to ensure constants are copied into registers when needed.
|
|
/// Remember the virtual registers that need to be added to the Machine PHI
|
|
/// nodes as input. We cannot just directly add them, because expansion might
|
|
/// result in multiple MBB's for one BB. As such, the start of the BB might
|
|
/// correspond to a different MBB than the end.
|
|
bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
|
|
|
|
/// \brief Helper for materializeRegForValue to materialize a constant in a
|
|
/// target-independent way.
|
|
unsigned materializeConstant(const Value *V, MVT VT);
|
|
|
|
/// \brief Helper for getRegForVale. This function is called when the value
|
|
/// isn't already available in a register and must be materialized with new
|
|
/// instructions.
|
|
unsigned materializeRegForValue(const Value *V, MVT VT);
|
|
|
|
/// \brief Clears LocalValueMap and moves the area for the new local variables
|
|
/// to the beginning of the block. It helps to avoid spilling cached variables
|
|
/// across heavy instructions like calls.
|
|
void flushLocalValueMap();
|
|
|
|
/// \brief Insertion point before trying to select the current instruction.
|
|
MachineBasicBlock::iterator SavedInsertPt;
|
|
|
|
/// \brief Add a stackmap or patchpoint intrinsic call's live variable
|
|
/// operands to a stackmap or patchpoint machine instruction.
|
|
bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
|
|
const CallInst *CI, unsigned StartIdx);
|
|
bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
|
|
const Value *Callee, bool ForceRetVoidTy,
|
|
CallLoweringInfo &CLI);
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|