mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 01:10:48 +00:00
d9e70873f3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180003 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
4.4 KiB
LLVM
199 lines
4.4 KiB
LLVM
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
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@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
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@i3 = common global i32* null, align 4
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; O32: lw $[[R0:[0-9]+]], %got(i3)
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; O32: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
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; O32: movn $[[R0]], $[[R1]], ${{[0-9]+}}
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; N64: ldr $[[R0:[0-9]+]]
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; N64: ld $[[R1:[0-9]+]], %got_disp(i1)
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; N64: movn $[[R0]], $[[R1]], ${{[0-9]+}}
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define i32* @cmov1(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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%tmp1 = load i32** @i3, align 4
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%cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
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ret i32* %cond
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}
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@c = global i32 1, align 4
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@d = global i32 0, align 4
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; O32: cmov2:
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; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
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; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
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; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
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; N64: cmov2:
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; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
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; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
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; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
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define i32 @cmov2(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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%tmp1 = load i32* @c, align 4
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%tmp2 = load i32* @d, align 4
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%cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
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ret i32 %cond
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}
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; O32: cmov3:
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; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i32 %b, i32 %c
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ret i32 %cond
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}
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; N64: cmov4:
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; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i64 %b, i64 %c
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ret i64 %cond
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}
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; slti and conditional move.
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;
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; Check that, pattern
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; (select (setgt a, N), t, f)
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; turns into
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; (movz t, (setlt a, N + 1), f)
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; if N + 1 fits in 16-bit.
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; O32: slti0:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti0(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti1:
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; O32: slt ${{[0-9]+}}
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define i32 @slti1(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti2:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti2(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti3:
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; O32: slt ${{[0-9]+}}
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define i32 @slti3(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; 64-bit patterns.
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; N64: slti64_0:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_0(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32766
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_1:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_1(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32767
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_2:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_2(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32769
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_3:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_3(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32770
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; sltiu instructions.
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; O32: sltiu0:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu0(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu1:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu1(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu2:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu2(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu3:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu3(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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