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tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
4.3 KiB
TableGen
100 lines
4.3 KiB
TableGen
//====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes FMA (Fused Multiply-Add) instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FMA3 - Intel 3 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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multiclass fma_rm<bits<8> opc, string OpcodeStr> {
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>;
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}
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multiclass fma_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpcodeStr, string PackTy> {
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defm r132 : fma_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
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defm r213 : fma_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
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defm r231 : fma_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
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}
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let isAsmParserOnly = 1 in {
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// Fused Multiply-Add
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defm VFMADDPS : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
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defm VFMADDPD : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
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defm VFMADDSUBPS : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
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defm VFMADDSUBPD : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
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defm VFMSUBADDPS : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
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defm VFMSUBADDPD : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
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defm VFMSUBPS : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
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defm VFMSUBPD : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
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// Fused Negative Multiply-Add
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defm VFNMADDPS : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
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defm VFNMADDPD : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
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defm VFNMSUBPS : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
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defm VFNMSUBPD : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
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}
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//===----------------------------------------------------------------------===//
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// FMA4 - AMD 4 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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multiclass fma4s<bits<8> opc, string OpcodeStr> {
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def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
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[]>, XOP_W;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>;
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}
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let isAsmParserOnly = 1 in {
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd">;
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}
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// FMA4 Intrinsics patterns
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2,
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(alignedloadv2f64 addr:$src3)),
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(VFMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
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VR128:$src3),
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(VFMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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