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a TargetMachine since the only thing it wants is DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210366 91177308-0d34-0410-b5e6-96231b3b80d8
223 lines
7.6 KiB
C++
223 lines
7.6 KiB
C++
//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXTargetMachine.h"
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#include "MCTargetDesc/NVPTXMCAsmInfo.h"
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#include "NVPTX.h"
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#include "NVPTXAllocaHoisting.h"
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#include "NVPTXLowerAggrCopies.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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namespace llvm {
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void initializeNVVMReflectPass(PassRegistry&);
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void initializeGenericToNVVMPass(PassRegistry&);
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void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
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void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
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}
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extern "C" void LLVMInitializeNVPTXTarget() {
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// Register the target.
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RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
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RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
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// FIXME: This pass is really intended to be invoked during IR optimization,
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// but it's very NVPTX-specific.
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initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
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initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
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initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
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initializeNVPTXFavorNonGenericAddrSpacesPass(
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*PassRegistry::getPassRegistry());
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}
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static std::string computeDataLayout(const NVPTXSubtarget &ST) {
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std::string Ret = "e";
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if (!ST.is64Bit())
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Ret += "-p:32:32";
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Ret += "-i64:64-v16:16-v32:32-n16:32:64";
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return Ret;
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}
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NVPTXTargetMachine::NVPTXTargetMachine(
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const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
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InstrInfo(*this), TLInfo(*this), TSInfo(&DL),
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FrameLowering(
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*this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
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initAsmInfo();
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}
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void NVPTXTargetMachine32::anchor() {}
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NVPTXTargetMachine32::NVPTXTargetMachine32(
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const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void NVPTXTargetMachine64::anchor() {}
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NVPTXTargetMachine64::NVPTXTargetMachine64(
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const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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namespace {
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class NVPTXPassConfig : public TargetPassConfig {
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public:
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NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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NVPTXTargetMachine &getNVPTXTargetMachine() const {
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return getTM<NVPTXTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addFastRegAlloc(FunctionPass *RegAllocPass) override;
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void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
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};
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} // end anonymous namespace
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TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
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return PassConfig;
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}
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void NVPTXPassConfig::addIRPasses() {
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// The following passes are known to not play well with virtual regs hanging
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// around after register allocation (which in our case, is *all* registers).
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// We explicitly disable them here. We do, however, need some functionality
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// of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
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// NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
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disablePass(&PrologEpilogCodeInserterID);
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disablePass(&MachineCopyPropagationID);
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disablePass(&BranchFolderPassID);
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disablePass(&TailDuplicateID);
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addPass(createNVPTXImageOptimizerPass());
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TargetPassConfig::addIRPasses();
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addPass(createNVPTXAssignValidGlobalNamesPass());
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addPass(createGenericToNVVMPass());
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addPass(createNVPTXFavorNonGenericAddrSpacesPass());
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addPass(createSeparateConstOffsetFromGEPPass());
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// The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
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// by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
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// significantly better code than EarlyCSE for some of our benchmarks.
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if (getOptLevel() == CodeGenOpt::Aggressive)
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addPass(createGVNPass());
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else
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addPass(createEarlyCSEPass());
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// Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
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// some dead code. We could remove dead code in an ad-hoc manner, but that
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// requires manual work and might be error-prone.
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//
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// The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
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// and leave them unused.
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//
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// SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
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// old index and some of its intermediate results may become unused.
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addPass(createDeadCodeEliminationPass());
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}
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bool NVPTXPassConfig::addInstSelector() {
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const NVPTXSubtarget &ST =
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getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
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addPass(createLowerAggrCopies());
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addPass(createAllocaHoisting());
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addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
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if (!ST.hasImageHandles())
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addPass(createNVPTXReplaceImageHandlesPass());
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return false;
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}
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bool NVPTXPassConfig::addPreRegAlloc() { return false; }
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bool NVPTXPassConfig::addPostRegAlloc() {
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addPass(createNVPTXPrologEpilogPass());
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return false;
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}
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FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
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return nullptr; // No reg alloc
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}
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void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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assert(!RegAllocPass && "NVPTX uses no regalloc!");
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addPass(&PHIEliminationID);
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addPass(&TwoAddressInstructionPassID);
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}
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void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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assert(!RegAllocPass && "NVPTX uses no regalloc!");
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addPass(&ProcessImplicitDefsID);
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addPass(&LiveVariablesID);
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addPass(&MachineLoopInfoID);
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addPass(&PHIEliminationID);
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addPass(&TwoAddressInstructionPassID);
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addPass(&RegisterCoalescerID);
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// PreRA instruction scheduling.
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if (addPass(&MachineSchedulerID))
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printAndVerify("After Machine Scheduling");
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addPass(&StackSlotColoringID);
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// FIXME: Needs physical registers
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//addPass(&PostRAMachineLICMID);
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printAndVerify("After StackSlotColoring");
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}
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