mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
3.5 KiB
C++
113 lines
3.5 KiB
C++
//===-- MipsTargetMachine.h - Define TargetMachine for Mips -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSTARGETMACHINE_H
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#define MIPSTARGETMACHINE_H
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#include "MipsFrameLowering.h"
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#include "MipsISelLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsJITInfo.h"
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#include "MipsSelectionDAGInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetTransformImpl.h"
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namespace llvm {
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class formatted_raw_ostream;
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class MipsRegisterInfo;
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class MipsTargetMachine : public LLVMTargetMachine {
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MipsSubtarget Subtarget;
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const DataLayout DL; // Calculates type size & alignment
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OwningPtr<const MipsInstrInfo> InstrInfo;
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OwningPtr<const MipsFrameLowering> FrameLowering;
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MipsTargetLowering TLInfo;
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MipsSelectionDAGInfo TSInfo;
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MipsJITInfo JITInfo;
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ScalarTargetTransformImpl STTI;
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VectorTargetTransformImpl VTTI;
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public:
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool isLittle);
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virtual ~MipsTargetMachine() {}
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virtual const MipsInstrInfo *getInstrInfo() const
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{ return InstrInfo.get(); }
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virtual const TargetFrameLowering *getFrameLowering() const
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{ return FrameLowering.get(); }
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virtual const MipsSubtarget *getSubtargetImpl() const
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{ return &Subtarget; }
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virtual const DataLayout *getDataLayout() const
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{ return &DL;}
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virtual MipsJITInfo *getJITInfo()
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{ return &JITInfo; }
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virtual const MipsRegisterInfo *getRegisterInfo() const {
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return &InstrInfo->getRegisterInfo();
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}
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virtual const MipsTargetLowering *getTargetLowering() const {
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return &TLInfo;
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}
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virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
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return &STTI;
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}
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virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
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return &VTTI;
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}
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
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};
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/// MipsebTargetMachine - Mips32/64 big endian target machine.
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///
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class MipsebTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// MipselTargetMachine - Mips32/64 little endian target machine.
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///
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class MipselTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // End llvm namespace
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#endif
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