llvm-6502/lib/CodeGen
2012-10-04 22:35:15 +00:00
..
AsmPrinter Update this a bit more to represent how the prologue should work: 2012-10-04 20:46:14 +00:00
SelectionDAG When merging connsecutive stores, use vectors to store the constant zero. 2012-10-04 22:35:15 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Convert some attribute existence queries over to use the predicate methods. 2012-09-19 23:54:18 +00:00
AntiDepBreaker.h
BranchFolding.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
BranchFolding.h
CalcSpillWeights.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
CallingConvLower.cpp
CMakeLists.txt Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodeGen.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodePlacementOpt.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DFAPacketizer.cpp
DwarfEHPrepare.cpp
EarlyIfConversion.cpp Get MCSchedModel directly from the subtarget. 2012-10-04 17:30:43 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to not propagate through implicit defs. 2012-10-03 08:29:36 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
InlineSpiller.cpp Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses an instruction's use of a physical register, analogous to analyzeVirtReg. 2012-09-12 10:03:31 +00:00
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp
LiveDebugVariables.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
LiveDebugVariables.h
LiveInterval.cpp Don't dereference begin() on an empty vector. 2012-09-27 21:05:59 +00:00
LiveIntervalAnalysis.cpp Handle reserved registers more accurately in handleMove(). 2012-10-02 22:08:36 +00:00
LiveIntervalUnion.cpp
LiveIntervalUnion.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00
LiveRangeCalc.cpp Clear kill flags while computing live ranges. 2012-09-06 18:15:15 +00:00
LiveRangeCalc.h
LiveRangeEdit.cpp Avoid dereferencing a NULL pointer. 2012-09-27 16:34:19 +00:00
LiveRegMatrix.cpp Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
LiveRegMatrix.h comment typo 2012-09-18 22:57:42 +00:00
LiveStackAnalysis.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
LiveVariables.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 2012-09-18 16:08:49 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Add a function computeRegisterLiveness() to MachineBasicBlock. This uses analyzePhysReg() from r163694 to heuristically try and determine the liveness state of a physical register upon arrival at a particular instruction in a block. 2012-09-12 10:18:23 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp
MachineDominators.cpp
MachineFunction.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Fix PR11985 2012-09-12 21:43:09 +00:00
MachineInstrBundle.cpp Increase the static sizes of some SmallSets. finalizeBundle() is very frequently called for some backends, and growing into an std::set is overkill for these numbers. 2012-09-17 18:31:15 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
MachineLoopRanges.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp Rename virtual table anchors from Anchor() to anchor() for consistency with the rest of the tree. 2012-09-26 06:36:36 +00:00
MachinePassRegistry.cpp
MachinePostDominators.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
MachineRegisterInfo.cpp
MachineScheduler.cpp misched: add a hook for custom DAG postprocessing. 2012-09-14 17:22:42 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp Switch MachineTraceMetrics to the new TargetSchedModel interface. 2012-10-04 17:30:40 +00:00
MachineTraceMetrics.h Switch MachineTraceMetrics to the new TargetSchedModel interface. 2012-10-04 17:30:40 +00:00
MachineVerifier.cpp Stop casting away const qualifier needlessly. 2012-09-05 22:26:57 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp The early if conversion pass is ready to be used as an opt-in. 2012-10-03 00:51:32 +00:00
PeepholeOptimizer.cpp
PHIElimination.cpp
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ProcessImplicitDefs.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
PrologEpilogInserter.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocFast.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocGreedy.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
RegAllocPBQP.cpp Fix reg mask slot test, and preserve LiveIntervals and VirtRegMap in the PBQP 2012-10-04 04:50:53 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp Remove the old coalescer algorithm. 2012-10-02 22:45:03 +00:00
RegisterCoalescer.h Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
RegisterPressure.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ScheduleDAGInstrs.cpp misched: Make ScheduleDAGInstrs use the TargetSchedule interface. 2012-09-18 18:20:00 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ShadowStackGC.cpp
ShrinkWrapping.cpp
SjLjEHPrepare.cpp IRBuilderify the SjlLjEHPrepare pass. 2012-09-03 12:27:43 +00:00
SlotIndexes.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
Spiller.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
SplitKit.h
StackColoring.cpp Disable the protection from escaped allocas in an attempt to find violating passes. This may break the buildbots. I plan to revert it in a few hours. 2012-09-17 10:21:55 +00:00
StackProtector.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
StackSlotColoring.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
StrongPHIElimination.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
TailDuplication.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfoImpl.cpp TargetSchedModel API. Implement latency lookup, disabled. 2012-09-18 04:03:34 +00:00
TargetLoweringObjectFileImpl.cpp
TargetOptionsImpl.cpp
TargetSchedule.cpp Enable -schedmodel, but prefer itineraries until we have more benchmark data. 2012-10-04 00:24:34 +00:00
TwoAddressInstructionPass.cpp Stop adding <imp-def> operands when expanding REG_SEQUENCE. 2012-09-17 23:03:21 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
VirtRegMap.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.