mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
1bc147c091
This adds all missing extended rotate/shift mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
1088 lines
34 KiB
C++
1088 lines
34 KiB
C++
//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCMCExpr.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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static unsigned RRegs[32] = {
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PPC::R0, PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static unsigned RRegsNoR0[32] = {
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PPC::ZERO,
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PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static unsigned XRegs[32] = {
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PPC::X0, PPC::X1, PPC::X2, PPC::X3,
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PPC::X4, PPC::X5, PPC::X6, PPC::X7,
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PPC::X8, PPC::X9, PPC::X10, PPC::X11,
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PPC::X12, PPC::X13, PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31
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};
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static unsigned XRegsNoX0[32] = {
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PPC::ZERO8,
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PPC::X1, PPC::X2, PPC::X3,
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PPC::X4, PPC::X5, PPC::X6, PPC::X7,
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PPC::X8, PPC::X9, PPC::X10, PPC::X11,
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PPC::X12, PPC::X13, PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31
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};
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static unsigned FRegs[32] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31
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};
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static unsigned VRegs[32] = {
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PPC::V0, PPC::V1, PPC::V2, PPC::V3,
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PPC::V4, PPC::V5, PPC::V6, PPC::V7,
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PPC::V8, PPC::V9, PPC::V10, PPC::V11,
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PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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PPC::V16, PPC::V17, PPC::V18, PPC::V19,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31
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};
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static unsigned CRBITRegs[32] = {
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PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
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PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
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PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
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PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
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};
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static unsigned CRRegs[8] = {
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PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
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PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
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};
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struct PPCOperand;
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class PPCAsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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bool IsPPC64;
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool isPPC64() const { return IsPPC64; }
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bool MatchRegisterName(const AsmToken &Tok,
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unsigned &RegNo, int64_t &IntVal);
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
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PPCMCExpr::VariantKind &Variant);
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bool ParseExpression(const MCExpr *&EVal);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveTC(unsigned Size, SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm);
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void ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "PPCGenAsmMatcher.inc"
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/// }
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public:
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PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
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: MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
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// Check for 64-bit vs. 32-bit pointer mode.
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Triple TheTriple(STI.getTargetTriple());
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IsPPC64 = TheTriple.getArch() == Triple::ppc64;
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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virtual bool ParseInstruction(ParseInstructionInfo &Info,
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StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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/// PPCOperand - Instances of this class represent a parsed PowerPC machine
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/// instruction.
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struct PPCOperand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Immediate,
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Expression
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} Kind;
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SMLoc StartLoc, EndLoc;
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bool IsPPC64;
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struct TokOp {
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const char *Data;
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unsigned Length;
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};
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struct ImmOp {
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int64_t Val;
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};
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struct ExprOp {
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const MCExpr *Val;
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};
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union {
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struct TokOp Tok;
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struct ImmOp Imm;
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struct ExprOp Expr;
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};
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PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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public:
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PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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IsPPC64 = o.IsPPC64;
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switch (Kind) {
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case Token:
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Tok = o.Tok;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Expression:
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Expr = o.Expr;
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break;
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}
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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/// isPPC64 - True if this operand is for an instruction in 64-bit mode.
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bool isPPC64() const { return IsPPC64; }
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int64_t getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getExpr() const {
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assert(Kind == Expression && "Invalid access!");
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return Expr.Val;
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}
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unsigned getReg() const {
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assert(isRegNumber() && "Invalid access!");
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return (unsigned) Imm.Val;
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}
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unsigned getCCReg() const {
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assert(isCCRegNumber() && "Invalid access!");
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return (unsigned) Imm.Val;
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}
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unsigned getCRBitMask() const {
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assert(isCRBitMask() && "Invalid access!");
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return 7 - countTrailingZeros<uint64_t>(Imm.Val);
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}
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bool isToken() const { return Kind == Token; }
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bool isImm() const { return Kind == Immediate || Kind == Expression; }
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bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
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bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
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bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
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bool isU16Imm() const { return Kind == Expression ||
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(Kind == Immediate && isUInt<16>(getImm())); }
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bool isS16Imm() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm())); }
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bool isS16ImmX4() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 3) == 0); }
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bool isDirectBr() const { return Kind == Expression ||
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(Kind == Immediate && isInt<26>(getImm()) &&
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(getImm() & 3) == 0); }
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bool isCondBr() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 3) == 0); }
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bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
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bool isCCRegNumber() const { return Kind == Immediate &&
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isUInt<3>(getImm()); }
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bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
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isPowerOf2_32(getImm()); }
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bool isMem() const { return false; }
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bool isReg() const { return false; }
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void addRegOperands(MCInst &Inst, unsigned N) const {
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llvm_unreachable("addRegOperands");
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}
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void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
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}
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void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
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}
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void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
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}
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void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
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}
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void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
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if (isPPC64())
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addRegG8RCOperands(Inst, N);
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else
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addRegGPRCOperands(Inst, N);
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}
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void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
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if (isPPC64())
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addRegG8RCNoX0Operands(Inst, N);
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else
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addRegGPRCNoR0Operands(Inst, N);
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}
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void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
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}
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void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
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}
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void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
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}
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void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getReg()]));
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}
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void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
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}
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void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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if (Kind == Immediate)
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Inst.addOperand(MCOperand::CreateImm(getImm()));
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else
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Inst.addOperand(MCOperand::CreateExpr(getExpr()));
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}
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void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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if (Kind == Immediate)
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Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
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else
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Inst.addOperand(MCOperand::CreateExpr(getExpr()));
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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virtual void print(raw_ostream &OS) const;
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static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
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PPCOperand *Op = new PPCOperand(Token);
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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Op->IsPPC64 = IsPPC64;
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return Op;
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}
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static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
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PPCOperand *Op = new PPCOperand(Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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Op->IsPPC64 = IsPPC64;
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return Op;
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}
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static PPCOperand *CreateExpr(const MCExpr *Val,
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SMLoc S, SMLoc E, bool IsPPC64) {
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PPCOperand *Op = new PPCOperand(Expression);
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Op->Expr.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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Op->IsPPC64 = IsPPC64;
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return Op;
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}
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};
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} // end anonymous namespace.
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void PPCOperand::print(raw_ostream &OS) const {
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switch (Kind) {
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case Token:
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OS << "'" << getToken() << "'";
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break;
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case Immediate:
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OS << getImm();
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break;
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case Expression:
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getExpr()->print(OS);
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break;
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}
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}
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void PPCAsmParser::
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ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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int Opcode = Inst.getOpcode();
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switch (Opcode) {
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case PPC::LAx: {
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MCInst TmpInst;
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TmpInst.setOpcode(PPC::LA);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(2));
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TmpInst.addOperand(Inst.getOperand(1));
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Inst = TmpInst;
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break;
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}
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case PPC::SUBI: {
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MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDI);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBIS: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDIS);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBIC: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDIC);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBICo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDICo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTLWI:
|
|
case PPC::EXTLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTRWI:
|
|
case PPC::EXTRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B + N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSLWI:
|
|
case PPC::INSLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSRWI:
|
|
case PPC::INSRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::ROTRWI:
|
|
case PPC::ROTRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SLWI:
|
|
case PPC::SLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SRWI:
|
|
case PPC::SRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRRWI:
|
|
case PPC::CLRRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRLSLWI:
|
|
case PPC::CLRLSLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t B = Inst.getOperand(2).getImm();
|
|
int64_t N = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTLDI:
|
|
case PPC::EXTLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTRDI:
|
|
case PPC::EXTRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B + N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSRDI:
|
|
case PPC::INSRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::ROTRDI:
|
|
case PPC::ROTRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SLDI:
|
|
case PPC::SLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(63 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SRDI:
|
|
case PPC::SRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRRDI:
|
|
case PPC::CLRRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(63 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRLSLDI:
|
|
case PPC::CLRLSLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t B = Inst.getOperand(2).getImm();
|
|
int64_t N = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
MCStreamer &Out, unsigned &ErrorInfo,
|
|
bool MatchingInlineAsm) {
|
|
MCInst Inst;
|
|
|
|
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
|
|
default: break;
|
|
case Match_Success:
|
|
// Post-process instructions (typically extended mnemonics)
|
|
ProcessInstruction(Inst, Operands);
|
|
Inst.setLoc(IDLoc);
|
|
Out.EmitInstruction(Inst);
|
|
return false;
|
|
case Match_MissingFeature:
|
|
return Error(IDLoc, "instruction use requires an option to be enabled");
|
|
case Match_MnemonicFail:
|
|
return Error(IDLoc, "unrecognized instruction mnemonic");
|
|
case Match_InvalidOperand: {
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (ErrorInfo != ~0U) {
|
|
if (ErrorInfo >= Operands.size())
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
|
|
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
|
|
}
|
|
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Implement any new match types added!");
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
|
|
if (Tok.is(AsmToken::Identifier)) {
|
|
StringRef Name = Tok.getString();
|
|
|
|
if (Name.equals_lower("lr")) {
|
|
RegNo = isPPC64()? PPC::LR8 : PPC::LR;
|
|
IntVal = 8;
|
|
return false;
|
|
} else if (Name.equals_lower("ctr")) {
|
|
RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
|
|
IntVal = 9;
|
|
return false;
|
|
} else if (Name.substr(0, 1).equals_lower("r") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
|
|
return false;
|
|
} else if (Name.substr(0, 1).equals_lower("f") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = FRegs[IntVal];
|
|
return false;
|
|
} else if (Name.substr(0, 1).equals_lower("v") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = VRegs[IntVal];
|
|
return false;
|
|
} else if (Name.substr(0, 2).equals_lower("cr") &&
|
|
!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
|
|
RegNo = CRRegs[IntVal];
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
StartLoc = Tok.getLoc();
|
|
EndLoc = Tok.getEndLoc();
|
|
RegNo = 0;
|
|
int64_t IntVal;
|
|
|
|
if (!MatchRegisterName(Tok, RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat identifier token.
|
|
return false;
|
|
}
|
|
|
|
return Error(StartLoc, "invalid register name");
|
|
}
|
|
|
|
/// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
|
|
/// the expression and check for VK_PPC_LO/HI/HA
|
|
/// symbol variants. If all symbols with modifier use the same
|
|
/// variant, return the corresponding PPCMCExpr::VariantKind,
|
|
/// and a modified expression using the default symbol variant.
|
|
/// Otherwise, return NULL.
|
|
const MCExpr *PPCAsmParser::
|
|
ExtractModifierFromExpr(const MCExpr *E,
|
|
PPCMCExpr::VariantKind &Variant) {
|
|
MCContext &Context = getParser().getContext();
|
|
Variant = PPCMCExpr::VK_PPC_None;
|
|
|
|
switch (E->getKind()) {
|
|
case MCExpr::Target:
|
|
case MCExpr::Constant:
|
|
return 0;
|
|
|
|
case MCExpr::SymbolRef: {
|
|
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
|
|
|
|
switch (SRE->getKind()) {
|
|
case MCSymbolRefExpr::VK_PPC_LO:
|
|
Variant = PPCMCExpr::VK_PPC_LO;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HI:
|
|
Variant = PPCMCExpr::VK_PPC_HI;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HA:
|
|
Variant = PPCMCExpr::VK_PPC_HA;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHER:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHER;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHERA:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHERA;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHEST:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHEST;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHESTA:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHESTA;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
|
|
}
|
|
|
|
case MCExpr::Unary: {
|
|
const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
|
|
const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
|
|
if (!Sub)
|
|
return 0;
|
|
return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
|
|
}
|
|
|
|
case MCExpr::Binary: {
|
|
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
|
|
PPCMCExpr::VariantKind LHSVariant, RHSVariant;
|
|
const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
|
|
const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
|
|
|
|
if (!LHS && !RHS)
|
|
return 0;
|
|
|
|
if (!LHS) LHS = BE->getLHS();
|
|
if (!RHS) RHS = BE->getRHS();
|
|
|
|
if (LHSVariant == PPCMCExpr::VK_PPC_None)
|
|
Variant = RHSVariant;
|
|
else if (RHSVariant == PPCMCExpr::VK_PPC_None)
|
|
Variant = LHSVariant;
|
|
else if (LHSVariant == RHSVariant)
|
|
Variant = LHSVariant;
|
|
else
|
|
return 0;
|
|
|
|
return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Invalid expression kind!");
|
|
}
|
|
|
|
/// Parse an expression. This differs from the default "parseExpression"
|
|
/// in that it handles complex \code @l/@ha \endcode modifiers.
|
|
bool PPCAsmParser::
|
|
ParseExpression(const MCExpr *&EVal) {
|
|
if (getParser().parseExpression(EVal))
|
|
return true;
|
|
|
|
PPCMCExpr::VariantKind Variant;
|
|
const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
|
|
if (E)
|
|
EVal = PPCMCExpr::Create(Variant, E, getParser().getContext());
|
|
|
|
return false;
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
const MCExpr *EVal;
|
|
PPCOperand *Op;
|
|
|
|
// Attempt to parse the next token as an immediate
|
|
switch (getLexer().getKind()) {
|
|
// Special handling for register names. These are interpreted
|
|
// as immediates corresponding to the register number.
|
|
case AsmToken::Percent:
|
|
Parser.Lex(); // Eat the '%'.
|
|
unsigned RegNo;
|
|
int64_t IntVal;
|
|
if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat the identifier token.
|
|
Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
return false;
|
|
}
|
|
return Error(S, "invalid register name");
|
|
|
|
// All other expressions
|
|
case AsmToken::LParen:
|
|
case AsmToken::Plus:
|
|
case AsmToken::Minus:
|
|
case AsmToken::Integer:
|
|
case AsmToken::Identifier:
|
|
case AsmToken::Dot:
|
|
case AsmToken::Dollar:
|
|
if (!ParseExpression(EVal))
|
|
break;
|
|
/* fall through */
|
|
default:
|
|
return Error(S, "unknown operand");
|
|
}
|
|
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(EVal))
|
|
Op = PPCOperand::CreateImm(CE->getValue(), S, E, isPPC64());
|
|
else
|
|
Op = PPCOperand::CreateExpr(EVal, S, E, isPPC64());
|
|
|
|
// Push the parsed operand into the list of operands
|
|
Operands.push_back(Op);
|
|
|
|
// Check for D-form memory operands
|
|
if (getLexer().is(AsmToken::LParen)) {
|
|
Parser.Lex(); // Eat the '('.
|
|
S = Parser.getTok().getLoc();
|
|
|
|
int64_t IntVal;
|
|
switch (getLexer().getKind()) {
|
|
case AsmToken::Percent:
|
|
Parser.Lex(); // Eat the '%'.
|
|
unsigned RegNo;
|
|
if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
|
|
return Error(S, "invalid register name");
|
|
Parser.Lex(); // Eat the identifier token.
|
|
break;
|
|
|
|
case AsmToken::Integer:
|
|
if (getParser().parseAbsoluteExpression(IntVal) ||
|
|
IntVal < 0 || IntVal > 31)
|
|
return Error(S, "invalid register number");
|
|
break;
|
|
|
|
default:
|
|
return Error(S, "invalid memory operand");
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return Error(Parser.getTok().getLoc(), "missing ')'");
|
|
E = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the ')'.
|
|
|
|
Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Parse an instruction mnemonic followed by its operands.
|
|
bool PPCAsmParser::
|
|
ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
// The first operand is the token for the instruction name.
|
|
// If the next character is a '+' or '-', we need to add it to the
|
|
// instruction name, to match what TableGen is doing.
|
|
if (getLexer().is(AsmToken::Plus)) {
|
|
getLexer().Lex();
|
|
char *NewOpcode = new char[Name.size() + 1];
|
|
memcpy(NewOpcode, Name.data(), Name.size());
|
|
NewOpcode[Name.size()] = '+';
|
|
Name = StringRef(NewOpcode, Name.size() + 1);
|
|
}
|
|
if (getLexer().is(AsmToken::Minus)) {
|
|
getLexer().Lex();
|
|
char *NewOpcode = new char[Name.size() + 1];
|
|
memcpy(NewOpcode, Name.data(), Name.size());
|
|
NewOpcode[Name.size()] = '-';
|
|
Name = StringRef(NewOpcode, Name.size() + 1);
|
|
}
|
|
// If the instruction ends in a '.', we need to create a separate
|
|
// token for it, to match what TableGen is doing.
|
|
size_t Dot = Name.find('.');
|
|
StringRef Mnemonic = Name.slice(0, Dot);
|
|
Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
|
|
if (Dot != StringRef::npos) {
|
|
SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
|
|
StringRef DotStr = Name.slice(Dot, StringRef::npos);
|
|
Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
|
|
}
|
|
|
|
// If there are no more operands then finish
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
return false;
|
|
|
|
// Parse the first operand
|
|
if (ParseOperand(Operands))
|
|
return true;
|
|
|
|
while (getLexer().isNot(AsmToken::EndOfStatement) &&
|
|
getLexer().is(AsmToken::Comma)) {
|
|
// Consume the comma token
|
|
getLexer().Lex();
|
|
|
|
// Parse the next operand
|
|
if (ParseOperand(Operands))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirective parses the PPC specific directives
|
|
bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(4, DirectiveID.getLoc());
|
|
if (IDVal == ".tc")
|
|
return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().parseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveTC
|
|
/// ::= .tc [ symbol (, expression)* ]
|
|
bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
|
|
// Skip TC symbol, which is only used with XCOFF.
|
|
while (getLexer().isNot(AsmToken::EndOfStatement)
|
|
&& getLexer().isNot(AsmToken::Comma))
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// Align to word size.
|
|
getParser().getStreamer().EmitValueToAlignment(Size);
|
|
|
|
// Emit expressions.
|
|
return ParseDirectiveWord(Size, L);
|
|
}
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializePowerPCAsmParser() {
|
|
RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
|
|
RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "PPCGenAsmMatcher.inc"
|