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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
701 lines
28 KiB
C++
701 lines
28 KiB
C++
//===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines stuff that is to be private to the Sparc backend, but is
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// shared among different portions of the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSchedInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetCacheInfo.h"
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#include "llvm/Target/TargetRegInfo.h"
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#include "llvm/Type.h"
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#include "SparcRegClassInfo.h"
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#include "Config/sys/types.h"
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namespace llvm {
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class LiveRange;
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class UltraSparc;
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class Pass;
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enum SparcInstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const TargetInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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namespace V9 {
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enum SparcMachineOpCode {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcInstr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = PHI, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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}
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// Array of machine instruction descriptions...
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extern const TargetInstrDescriptor SparcMachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class TargetInstrInfo.
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//---------------------------------------------------------------------------
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struct UltraSparcInstrInfo : public TargetInstrInfo {
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UltraSparcInstrInfo();
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//
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// All immediate constants are in position 1 except the
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// store instructions and SETxx.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0) {
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// 1st store opcode
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assert(! this->isStore((MachineOpCode) V9::STBr - 1));
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// last store opcode
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assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
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if (opCode == V9::SETSW || opCode == V9::SETUW ||
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opCode == V9::SETX || opCode == V9::SETHI)
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return 0;
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if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
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return 2;
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return 1;
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}
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else
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return -1;
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}
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
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///
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MachineInstr* createNOPinstr() const {
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return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `sethi g0, 0'
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if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isImmediate() && op0.getImmedValue() == 0 &&
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op1.isMachineRegister() &&
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op1.getMachineRegNum() == SparcIntRegClass::g0)
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{
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return true;
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}
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}
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return false;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
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}
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//-------------------------------------------------------------------------
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// Queries about representation of LLVM quantities (e.g., constants)
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//-------------------------------------------------------------------------
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virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
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const Instruction* I) const;
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. This and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
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// Get the value of an integral constant in the form that must
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// be put into the machine register. The specified constant is interpreted
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// as (i.e., converted if necessary to) the specified destination type. The
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// result is always returned as an uint64_t, since the representation of
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// int64_t and uint64_t are identical. The argument can be any known const.
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//
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// isValidConstant is set to true if a valid constant was found.
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//
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virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
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const Value *V,
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const Type *destType,
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bool &isValidConstant) const;
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateSignExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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};
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//----------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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// This class implements the virtual class TargetRegInfo for Sparc.
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//
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//----------------------------------------------------------------------------
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class UltraSparcRegInfo : public TargetRegInfo {
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private:
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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//
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unsigned const NumOfIntArgRegs;
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// Number of registers used for passing float args (usually 32: %f0 - %f31)
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//
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unsigned const NumOfFloatArgRegs;
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// ======================== Private Methods =============================
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// The following methods are used to color special live ranges (e.g.
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// function args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation.
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//
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void suggestReg4RetAddr(MachineInstr *RetMI,
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LiveRangeInfo &LRI) const;
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void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
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// Helper used by the all the getRegType() functions.
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int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
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public:
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// Type of registers available in Sparc. There can be several reg types
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// in the same class. For instace, the float reg class has Single/Double
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// types
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//
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enum RegTypes {
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IntRegType,
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FPSingleRegType,
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FPDoubleRegType,
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IntCCRegType,
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FloatCCRegType,
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SpecialRegType
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};
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// The actual register classes in the Sparc
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//
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// **** WARNING: If this enum order is changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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//
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enum RegClassIDs {
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IntRegClassID, // Integer
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FloatRegClassID, // Float (both single/double)
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IntCCRegClassID, // Int Condition Code
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FloatCCRegClassID, // Float Condition code
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SpecialRegClassID // Special (unallocated) registers
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};
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UltraSparcRegInfo(const UltraSparc &tgt);
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// To find the register class used for a specified Type
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//
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unsigned getRegClassIDOfType(const Type *type,
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bool isCCReg = false) const;
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// To find the register class to which a specified register belongs
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//
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unsigned getRegClassIDOfRegType(int regType) const;
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// getZeroRegNum - returns the register that contains always zero this is the
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// unified register number
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//
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virtual int getZeroRegNum() const;
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// getCallAddressReg - returns the reg used for pushing the address when a
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// function is called. This can be used for other purposes between calls
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//
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unsigned getCallAddressReg() const;
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// Returns the register containing the return address.
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// It should be made sure that this register contains the return
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// value when a return instruction is reached.
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//
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unsigned getReturnAddressReg() const;
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// Number of registers used for passing int args (usually 6: %o0 - %o5)
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// and float args (usually 32: %f0 - %f31)
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//
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unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
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unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
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// Compute which register can be used for an argument, if any
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//
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int regNumForIntArg(bool inCallee, bool isVarArgsCall,
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unsigned argNo, unsigned& regClassId) const;
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int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
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unsigned argNo, unsigned& regClassId) const;
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// The following methods are used to color special live ranges (e.g.
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// function args and return values etc.) with specific hardware registers
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// as required. See SparcRegInfo.cpp for the implementation for Sparc.
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//
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void suggestRegs4MethodArgs(const Function *Meth,
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LiveRangeInfo& LRI) const;
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void suggestRegs4CallArgs(MachineInstr *CallMI,
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LiveRangeInfo& LRI) const;
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void suggestReg4RetValue(MachineInstr *RetMI,
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LiveRangeInfo& LRI) const;
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void colorMethodArgs(const Function *Meth, LiveRangeInfo& LRI,
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std::vector<MachineInstr*>& InstrnsBefore,
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std::vector<MachineInstr*>& InstrnsAfter) const;
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// method used for printing a register for debugging purposes
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//
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void printReg(const LiveRange *LR) const;
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// returns the # of bytes of stack space allocated for each register
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// type. For Sparc, currently we allocate 8 bytes on stack for all
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// register types. We can optimize this later if necessary to save stack
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// space (However, should make sure that stack alignment is correct)
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//
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inline int getSpilledRegSize(int RegType) const {
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return 8;
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}
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// To obtain the return value and the indirect call address (if any)
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// contained in a CALL machine instruction
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//
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const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
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const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
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// The following methods are used to generate "copy" machine instructions
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// for an architecture.
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//
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// The function regTypeNeedsScratchReg() can be used to check whether a
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// scratch register is needed to copy a register of type `regType' to
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// or from memory. If so, such a scratch register can be provided by
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// the caller (e.g., if it knows which regsiters are free); otherwise
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// an arbitrary one will be chosen and spilled by the copy instructions.
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//
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bool regTypeNeedsScratchReg(int RegType,
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int& scratchRegClassId) const;
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void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg, unsigned DestReg,
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int RegType) const;
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void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg, unsigned DestPtrReg,
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int Offset, int RegType, int scratchReg = -1) const;
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void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcPtrReg, int Offset, unsigned DestReg,
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int RegType, int scratchReg = -1) const;
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void cpValue2Value(Value *Src, Value *Dest,
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std::vector<MachineInstr*>& mvec) const;
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// Get the register type for a register identified different ways.
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// Note that getRegTypeForLR(LR) != getRegTypeForDataType(LR->getType())!
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// The reg class of a LR depends both on the Value types in it and whether
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// they are CC registers or not (for example).
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int getRegTypeForDataType(const Type* type) const;
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int getRegTypeForLR(const LiveRange *LR) const;
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int getRegType(int unifiedRegNum) const;
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virtual unsigned getFramePointer() const;
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virtual unsigned getStackPointer() const;
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};
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//---------------------------------------------------------------------------
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// class UltraSparcSchedInfo
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//
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// Purpose:
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// Interface to instruction scheduling information for UltraSPARC.
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// The parameter values above are based on UltraSPARC IIi.
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//---------------------------------------------------------------------------
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class UltraSparcSchedInfo: public TargetSchedInfo {
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public:
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UltraSparcSchedInfo(const TargetMachine &tgt);
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protected:
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virtual void initializeResources();
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};
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//---------------------------------------------------------------------------
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// class UltraSparcFrameInfo
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//
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// Purpose:
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// Interface to stack frame layout info for the UltraSPARC.
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// Starting offsets for each area of the stack frame are aligned at
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// a multiple of getStackFrameSizeAlignment().
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//---------------------------------------------------------------------------
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class UltraSparcFrameInfo: public TargetFrameInfo {
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const TargetMachine ⌖
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public:
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UltraSparcFrameInfo(const TargetMachine &TM)
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: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
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public:
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// These methods provide constant parameters of the frame layout.
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//
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int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
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int getMinStackFrameSize() const { return MinStackFrameSize; }
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int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
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int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
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bool argsOnStackHaveFixedSize() const { return true; }
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// This method adjusts a stack offset to meet alignment rules of target.
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// The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
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virtual int adjustAlignment (int unalignedOffset,
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bool growUp,
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unsigned int align) const {
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return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
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}
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// These methods compute offsets using the frame contents for a
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// particular function. The frame contents are obtained from the
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// MachineCodeInfoForMethod object for the given function.
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//
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int getFirstIncomingArgOffset (MachineFunction& mcInfo,
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bool& growUp) const
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{
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growUp = true; // arguments area grows upwards
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|
return FirstIncomingArgOffsetFromFP;
|
|
}
|
|
int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const
|
|
{
|
|
growUp = true; // arguments area grows upwards
|
|
return FirstOutgoingArgOffsetFromSP;
|
|
}
|
|
int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
|
|
bool& growUp)const
|
|
{
|
|
growUp = true; // arguments area grows upwards
|
|
return FirstOptionalOutgoingArgOffsetFromSP;
|
|
}
|
|
|
|
int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getRegSpillAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getTmpAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
int getDynamicAreaOffset (MachineFunction& mcInfo,
|
|
bool& growUp) const;
|
|
|
|
//
|
|
// These methods specify the base register used for each stack area
|
|
// (generally FP or SP)
|
|
//
|
|
virtual int getIncomingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getOptionalOutgoingArgBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
virtual int getAutomaticVarBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getRegSpillAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getFramePointer();
|
|
}
|
|
virtual int getDynamicAreaBaseRegNum() const {
|
|
return (int) target.getRegInfo().getStackPointer();
|
|
}
|
|
|
|
virtual int getIncomingArgOffset(MachineFunction& mcInfo,
|
|
unsigned argNum) const {
|
|
assert(argsOnStackHaveFixedSize());
|
|
|
|
unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
|
|
bool growUp; // do args grow up or down
|
|
int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
|
|
return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
|
|
}
|
|
|
|
virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
|
|
unsigned argNum) const {
|
|
assert(argsOnStackHaveFixedSize());
|
|
//assert(((int) argNum - this->getNumFixedOutgoingArgs())
|
|
// <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
|
|
|
|
unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
|
|
bool growUp; // do args grow up or down
|
|
int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
|
|
return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
|
|
}
|
|
|
|
private:
|
|
/*----------------------------------------------------------------------
|
|
This diagram shows the stack frame layout used by llc on Sparc V9.
|
|
Note that only the location of automatic variables, spill area,
|
|
temporary storage, and dynamically allocated stack area are chosen
|
|
by us. The rest conform to the Sparc V9 ABI.
|
|
All stack addresses are offset by OFFSET = 0x7ff (2047).
|
|
|
|
Alignment assumptions and other invariants:
|
|
(1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
|
|
(2) Variables in automatic, spill, temporary, or dynamic regions
|
|
are aligned according to their size as in all memory accesses.
|
|
(3) Everything below the dynamically allocated stack area is only used
|
|
during a call to another function, so it is never needed when
|
|
the current function is active. This is why space can be allocated
|
|
dynamically by incrementing %sp any time within the function.
|
|
|
|
STACK FRAME LAYOUT:
|
|
|
|
...
|
|
%fp+OFFSET+176 Optional extra incoming arguments# 1..N
|
|
%fp+OFFSET+168 Incoming argument #6
|
|
... ...
|
|
%fp+OFFSET+128 Incoming argument #1
|
|
... ...
|
|
---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
|
|
%fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
|
|
Spill area
|
|
Temporary storage
|
|
...
|
|
|
|
%sp+OFFSET+176+8N Bottom of dynamically allocated stack area
|
|
%sp+OFFSET+168+8N Optional extra outgoing argument# N
|
|
... ...
|
|
%sp+OFFSET+176 Optional extra outgoing argument# 1
|
|
%sp+OFFSET+168 Outgoing argument #6
|
|
... ...
|
|
%sp+OFFSET+128 Outgoing argument #1
|
|
%sp+OFFSET+120 Save area for %i7
|
|
... ...
|
|
%sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
// All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
|
|
static const int OFFSET = (int) 0x7ff;
|
|
static const int StackFrameSizeAlignment = 16;
|
|
static const int MinStackFrameSize = 176;
|
|
static const int NumFixedOutgoingArgs = 6;
|
|
static const int SizeOfEachArgOnStack = 8;
|
|
static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
|
|
static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
|
|
static const int StaticAreaOffsetFromFP = 0 + OFFSET;
|
|
static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
|
|
static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcCacheInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to cache parameters for the UltraSPARC.
|
|
// Just use defaults for now.
|
|
//---------------------------------------------------------------------------
|
|
|
|
struct UltraSparcCacheInfo: public TargetCacheInfo {
|
|
UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
|
|
};
|
|
|
|
|
|
/// createStackSlotsPass - External interface to stack-slots pass that enters 2
|
|
/// empty slots at the top of each function stack
|
|
Pass *createStackSlotsPass(const TargetMachine &TM);
|
|
|
|
// Interface to pre-selection pass that specializes LLVM code for a target
|
|
// machine.
|
|
FunctionPass *createPreSelectionPass(const TargetMachine &TM);
|
|
|
|
// External interface to peephole optimization pass operating on machine code.
|
|
FunctionPass *createPeepholeOptsPass(const TargetMachine &TM);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparc
|
|
//
|
|
// Purpose:
|
|
// Primary interface to machine description for the UltraSPARC.
|
|
// Primarily just initializes machine-dependent parameters in
|
|
// class TargetMachine, and creates machine-dependent subclasses
|
|
// for classes such as InstrInfo, SchedInfo and RegInfo.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparc : public TargetMachine {
|
|
UltraSparcInstrInfo instrInfo;
|
|
UltraSparcSchedInfo schedInfo;
|
|
UltraSparcRegInfo regInfo;
|
|
UltraSparcFrameInfo frameInfo;
|
|
UltraSparcCacheInfo cacheInfo;
|
|
public:
|
|
UltraSparc();
|
|
|
|
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
|
|
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
|
|
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
|
|
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
|
|
virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
|
|
|
|
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
|
virtual bool addPassesToJITCompile(FunctionPassManager &PM);
|
|
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
|
MachineCodeEmitter &MCE);
|
|
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
|
|
|
// getPrologEpilogInsertionPass - Inserts prolog/epilog code.
|
|
FunctionPass* getPrologEpilogInsertionPass();
|
|
|
|
// getFunctionAsmPrinterPass - Writes out machine code for a single function
|
|
Pass* getFunctionAsmPrinterPass(std::ostream &Out);
|
|
|
|
// getModuleAsmPrinterPass - Writes generated machine code to assembly file.
|
|
Pass* getModuleAsmPrinterPass(std::ostream &Out);
|
|
|
|
// getBytecodeAsmPrinterPass - Emits final LLVM bytecode to assembly file.
|
|
Pass* getBytecodeAsmPrinterPass(std::ostream &Out);
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|