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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@587 91177308-0d34-0410-b5e6-96231b3b80d8
484 lines
14 KiB
C++
484 lines
14 KiB
C++
// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// MachineInstr.h
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//
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// Purpose:
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//
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//
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// Strategy:
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//
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// History:
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// 7/2/01 - Vikram Adve - Created
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//**************************************************************************/
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include <iterator>
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/NonCopyable.h"
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#include "llvm/Target/InstInfo.h"
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template<class _MI, class _V> class ValOpIterator;
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//---------------------------------------------------------------------------
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// class MachineOperand
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//
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// Purpose:
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// Representation of each machine instruction operand.
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// This class is designed so that you can allocate a vector of operands
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// first and initialize each one later.
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//
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// E.g, for this VM instruction:
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// ptr = alloca type, numElements
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// we generate 2 machine instructions on the SPARC:
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//
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// mul Constant, Numelements -> Reg
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// add %sp, Reg -> Ptr
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//
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// Each instruction has 3 operands, listed above. Of those:
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// - Reg, NumElements, and Ptr are of operand type MO_Register.
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// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
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//
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// For the register operands, the virtual register type is as follows:
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//
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// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
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// MachineInstr* minstr will point to the instruction that computes reg.
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//
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// - %sp will be of virtual register type MO_MachineReg.
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// The field regNum identifies the machine register.
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//
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// - NumElements will be of virtual register type MO_VirtualReg.
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// The field Value* value identifies the value.
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//
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// - Ptr will also be of virtual register type MO_VirtualReg.
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// Again, the field Value* value identifies the value.
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//
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//---------------------------------------------------------------------------
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class MachineOperand {
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public:
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enum MachineOperandType {
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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};
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private:
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MachineOperandType opType;
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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unsigned int regNum; // register number for an explicit register
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int64_t immedVal; // constant value for an explicit constant
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};
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bool isDef; // is this a defition for the value
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// made public for faster access
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public:
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/*ctor*/ MachineOperand ();
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/*ctor*/ MachineOperand (MachineOperandType operandType,
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Value* _val);
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/*copy ctor*/ MachineOperand (const MachineOperand&);
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/*dtor*/ ~MachineOperand () {}
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// Accessor methods. Caller is responsible for checking the
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// operand type before invoking the corresponding accessor.
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//
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inline MachineOperandType getOperandType () const {
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return opType;
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}
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inline Value* getVRegValue () const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_PCRelativeDisp);
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return value;
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}
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inline unsigned int getMachineRegNum() const {
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assert(opType == MO_MachineRegister);
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return regNum;
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}
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inline int64_t getImmedValue () const {
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assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
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return immedVal;
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}
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inline bool opIsDef () const {
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return isDef;
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}
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public:
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friend ostream& operator<<(ostream& os, const MachineOperand& mop);
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private:
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// These functions are provided so that a vector of operands can be
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// statically allocated and individual ones can be initialized later.
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// Give class MachineInstr gets access to these functions.
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//
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void Initialize (MachineOperandType operandType,
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Value* _val);
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void InitializeConst (MachineOperandType operandType,
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int64_t intValue);
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void InitializeReg (unsigned int regNum);
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friend class MachineInstr;
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friend class ValOpIterator<const MachineInstr, const Value>;
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friend class ValOpIterator< MachineInstr, Value>;
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public:
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};
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inline
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MachineOperand::MachineOperand()
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: opType(MO_VirtualRegister),
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value(NULL),
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regNum(0),
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immedVal(0),
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isDef(false)
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{}
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inline
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MachineOperand::MachineOperand(MachineOperandType operandType,
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Value* _val)
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: opType(operandType),
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value(_val),
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regNum(0),
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immedVal(0),
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isDef(false)
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{}
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inline
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MachineOperand::MachineOperand(const MachineOperand& mo)
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: opType(mo.opType),
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isDef(false)
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{
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switch(opType) {
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case MO_VirtualRegister:
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case MO_CCRegister: value = mo.value; break;
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case MO_MachineRegister: regNum = mo.regNum; break;
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case MO_SignExtendedImmed:
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case MO_UnextendedImmed:
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case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
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default: assert(0);
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}
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}
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inline void
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MachineOperand::Initialize(MachineOperandType operandType,
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Value* _val)
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{
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opType = operandType;
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value = _val;
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}
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inline void
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MachineOperand::InitializeConst(MachineOperandType operandType,
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int64_t intValue)
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{
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opType = operandType;
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value = NULL;
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immedVal = intValue;
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}
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inline void
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MachineOperand::InitializeReg(unsigned int _regNum)
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{
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opType = MO_MachineRegister;
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value = NULL;
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regNum = _regNum;
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}
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//---------------------------------------------------------------------------
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// class MachineInstr
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//
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// Purpose:
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// Representation of each machine instruction.
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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//
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// opCodeMask is used to record variants of an instruction.
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// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
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// ANNUL: if 1: Annul delay slot instruction.
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// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
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// Instead of creating 4 different opcodes for BNZ, we create a single
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// opcode and set bits in opCodeMask for each of these flags.
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//---------------------------------------------------------------------------
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class MachineInstr : public NonCopyable {
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private:
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MachineOpCode opCode;
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OpCodeMask opCodeMask; // extra bits for variants of an opcode
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vector<MachineOperand> operands;
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public:
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typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
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typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
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public:
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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OpCodeMask _opCodeMask = 0x0);
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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unsigned numOperands,
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OpCodeMask _opCodeMask = 0x0);
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inline ~MachineInstr () {}
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const MachineOpCode getOpCode () const;
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unsigned int getNumOperands () const;
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const MachineOperand& getOperand (unsigned int i) const;
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MachineOperand& getOperand (unsigned int i);
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bool operandIsDefined(unsigned int i) const;
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void dump (unsigned int indent = 0) const;
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public:
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friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
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friend val_op_const_iterator;
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friend val_op_iterator;
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public:
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// Access to set the operands when building the machine instruction
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void SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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Value* _val, bool isDef=false);
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void SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue, bool isDef=false);
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void SetMachineOperand(unsigned int i,
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unsigned int regNum,
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bool isDef=false);
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};
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inline const MachineOpCode
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MachineInstr::getOpCode() const
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{
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return opCode;
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}
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inline unsigned int
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MachineInstr::getNumOperands() const
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{
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return operands.size();
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}
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inline MachineOperand&
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MachineInstr::getOperand(unsigned int i)
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{
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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inline const MachineOperand&
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MachineInstr::getOperand(unsigned int i) const
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{
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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inline bool
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MachineInstr::operandIsDefined(unsigned int i) const
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{
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return getOperand(i).opIsDef();
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}
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template<class _MI, class _V>
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class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
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private:
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unsigned int i;
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int resultPos;
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_MI* minstr;
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inline void skipToNextVal() {
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while (i < minstr->getNumOperands() &&
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! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
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|| minstr->operands[i].opType == MachineOperand::MO_CCRegister)
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&& minstr->operands[i].value != NULL))
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++i;
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}
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public:
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typedef ValOpIterator<_MI, _V> _Self;
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inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
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resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
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skipToNextVal();
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};
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inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
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const MachineOperand & getMachineOperand() const { return minstr->getOperand(i); }
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inline _V* operator->() const { return operator*(); }
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// inline bool isDef () const { return (((int) i) == resultPos); }
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inline bool isDef () const { return minstr->getOperand(i).isDef; }
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inline bool done () const { return (i == minstr->getNumOperands()); }
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inline _Self& operator++() { i++; skipToNextVal(); return *this; }
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inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
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};
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//---------------------------------------------------------------------------
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// class MachineCodeForVMInstr
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//
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// Purpose:
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// Representation of the sequence of machine instructions created
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// for a single VM instruction. Additionally records any temporary
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// "values" used as intermediate values in this sequence.
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// Note that such values should be treated as pure SSA values with
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// no interpretation of their operands (i.e., as a TmpInstruction object
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// which actually represents such a value).
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//
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//---------------------------------------------------------------------------
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class MachineCodeForVMInstr: public vector<MachineInstr*>
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{
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private:
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vector<Value*> tempVec;
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public:
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/*ctor*/ MachineCodeForVMInstr () {}
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/*ctor*/ ~MachineCodeForVMInstr ();
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const vector<Value*>&
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getTempValues () const { return tempVec; }
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void addTempValue (Value* val)
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{ tempVec.push_back(val); }
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// dropAllReferences() - This function drops all references within
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// temporary (hidden) instructions created in implementing the original
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// VM intruction. This ensures there are no remaining "uses" within
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// these hidden instructions, before the values of a method are freed.
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//
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// Make this inline because it has to be called from class Instruction
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// and inlining it avoids a serious circurality in link order.
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inline void dropAllReferences() {
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for (unsigned i=0, N=tempVec.size(); i < N; i++)
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if (Instruction *I = tempVec[i]->castInstruction())
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I->dropAllReferences();
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}
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};
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inline
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MachineCodeForVMInstr::~MachineCodeForVMInstr()
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{
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// Free the Value objects created to hold intermediate values
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for (unsigned i=0, N=tempVec.size(); i < N; i++)
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delete tempVec[i];
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// Free the MachineInstr objects allocated, if any.
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for (unsigned i=0, N=this->size(); i < N; i++)
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delete (*this)[i];
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}
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//---------------------------------------------------------------------------
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// class MachineCodeForBasicBlock
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//
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// Purpose:
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// Representation of the sequence of machine instructions created
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// for a basic block.
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//---------------------------------------------------------------------------
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class MachineCodeForBasicBlock: public vector<MachineInstr*> {
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public:
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typedef vector<MachineInstr*>::iterator iterator;
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typedef vector<const MachineInstr*>::const_iterator const_iterator;
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};
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//---------------------------------------------------------------------------
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// Target-independent utility routines for creating machine instructions
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//---------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated
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// "0" register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void Set2OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int resultPosition = 1);
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void Set3OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int op2Position = 1,
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int resultPosition = 2);
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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const TargetMachine& targetMachine,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue);
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ostream& operator<<(ostream& os, const MachineInstr& minstr);
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ostream& operator<<(ostream& os, const MachineOperand& mop);
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void PrintMachineInstructions (const Method *method);
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//**************************************************************************/
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#endif
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