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These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972 91177308-0d34-0410-b5e6-96231b3b80d8
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