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https://github.com/c64scene-ar/llvm-6502.git
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3c1dc3cac8
Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
815 B
LLVM
28 lines
815 B
LLVM
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s
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; CHECK-LABEL: main:
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; CHECK: pushl %esi
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; CHECK-NEXT: testb $1, 8(%esp)
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; CHECK-NEXT: movl $-12, %eax
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; CHECK-NEXT: movl $-1, %edx
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; CHECK-NEXT: cmovel %edx, %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: movl %eax, %esi
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; CHECK-NEXT: addl $-1, %esi
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; CHECK-NEXT: movl $-1, %esi
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; CHECK-NEXT: adcl $-1, %esi
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: cmovsl %ecx, %edx
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; CHECK-NEXT: popl %esi
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define i64 @main(i1 %tobool1) nounwind {
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entry:
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%0 = zext i1 %tobool1 to i32
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%. = xor i32 %0, 1
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%.21 = select i1 %tobool1, i32 -12, i32 -1
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%conv = sext i32 %.21 to i64
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%1 = add i64 %conv, -1
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%cmp10 = icmp slt i64 %1, 0
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%sub17 = select i1 %cmp10, i64 0, i64 %conv
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ret i64 %sub17
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}
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