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mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
1.1 KiB
TableGen
27 lines
1.1 KiB
TableGen
//===- MBlazeCallingConv.td - Calling Conventions for MBlaze -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for MBlaze architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>:
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CCIf<!strconcat("State.getTarget().getSubtarget<MBlazeSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// MBlaze ABI Calling Convention
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//===----------------------------------------------------------------------===//
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def RetCC_MBlaze : CallingConv<[
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// i32 are returned in registers R3, R4
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CCIfType<[i32], CCAssignToReg<[R3, R4]>>,
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// f32 are returned in registers R3, R4
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CCIfType<[f32], CCAssignToReg<[R3, R4]>>
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]>;
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