Elena Demikhovsky 1c21f2ef8c AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/D ... instructions. These intrinsics are comming with rounding mode. Added intrinsics for MAXSS/D, MINSS/D - with and without sae. By Asaf Badouh (asaf.badouh@intel.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237560 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-18 07:24:19 +00:00
..
AArch64	Mark SMIN/SMAX/UMIN/UMAX nodes as legal and add patterns for them.	2015-05-15 16:15:57 +00:00
ARM	[CodeGen] Use standard -not gnueabi- naming for f16 libcalls on Darwin.	2015-05-14 01:00:51 +00:00
BPF
CPP
Generic	[Statepoints] Support for "patchable" statepoints.	2015-05-12 23:52:24 +00:00
Hexagon	[Hexagon] Generate hardware loop for a vectorized loop	2015-05-14 20:36:19 +00:00
Inputs
Mips	[mips] Do not place users of $ra in the delay slot of call instructions.	2015-05-14 13:17:56 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add extra r2 read deps on @toc@l relocations	2015-05-18 06:25:59 +00:00
R600	R600/SI: add pass to mark CF live ranges as non-spillable	2015-05-12 17:13:02 +00:00
SPARC
SystemZ
Thumb
Thumb2
WinEH	Changed renaming of local symbols by inserting a dot vefore the numeric suffix.	2015-05-12 16:47:30 +00:00
X86	AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/D	2015-05-18 07:24:19 +00:00
XCore