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OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158244 91177308-0d34-0410-b5e6-96231b3b80d8
676 lines
26 KiB
C++
676 lines
26 KiB
C++
//===-- Passes.cpp - Target independent code generation passes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code
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// generation passes provided by the LLVM backend.
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//
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//===---------------------------------------------------------------------===//
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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cl::desc("Disable pre-register allocation tail duplication"));
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static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
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cl::Hidden, cl::desc("Disable the probability-driven block placement, and "
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"re-enable the old code placement pass"));
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static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
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cl::desc("Disable code placement"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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cl::desc("Disable Machine Dead Code Elimination"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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cl::desc("Disable Machine Common Subexpression Elimination"));
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static cl::opt<cl::boolOrDefault>
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OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
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cl::desc("Enable optimized register allocation compilation path."));
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static cl::opt<cl::boolOrDefault>
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EnableMachineSched("enable-misched", cl::Hidden,
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cl::desc("Enable the machine instruction scheduling pass."));
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static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
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cl::desc("Use strong PHI elimination."));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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static cl::opt<std::string>
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PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
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cl::desc("Print machine instrs"),
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cl::value_desc("pass-name"), cl::init("option-unspecified"));
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/// Allow standard passes to be disabled by command line options. This supports
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/// simple binary flags that either suppress the pass or do nothing.
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/// i.e. -disable-mypass=false has no effect.
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/// These should be converted to boolOrDefault in order to use applyOverride.
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static AnalysisID applyDisable(AnalysisID ID, bool Override) {
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if (Override)
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return &NoPassID;
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return ID;
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}
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/// Allow Pass selection to be overriden by command line options. This supports
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/// flags with ternary conditions. TargetID is passed through by default. The
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/// pass is suppressed when the option is false. When the option is true, the
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/// StandardID is selected if the target provides no default.
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static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
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AnalysisID StandardID) {
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switch (Override) {
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case cl::BOU_UNSET:
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return TargetID;
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case cl::BOU_TRUE:
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if (TargetID != &NoPassID)
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return TargetID;
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if (StandardID == &NoPassID)
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report_fatal_error("Target cannot enable pass");
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return StandardID;
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case cl::BOU_FALSE:
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return &NoPassID;
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}
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llvm_unreachable("Invalid command line option state");
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}
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/// Allow standard passes to be disabled by the command line, regardless of who
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/// is adding the pass.
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///
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/// StandardID is the pass identified in the standard pass pipeline and provided
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/// to addPass(). It may be a target-specific ID in the case that the target
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/// directly adds its own pass, but in that case we harmlessly fall through.
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///
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/// TargetID is the pass that the target has configured to override StandardID.
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///
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/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
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/// pass to run. This allows multiple options to control a single pass depending
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/// on where in the pipeline that pass is added.
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static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) {
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if (StandardID == &PostRASchedulerID)
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return applyDisable(TargetID, DisablePostRA);
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if (StandardID == &BranchFolderPassID)
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return applyDisable(TargetID, DisableBranchFold);
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if (StandardID == &TailDuplicateID)
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return applyDisable(TargetID, DisableTailDuplicate);
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if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
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return applyDisable(TargetID, DisableEarlyTailDup);
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if (StandardID == &MachineBlockPlacementID)
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return applyDisable(TargetID, DisableCodePlace);
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if (StandardID == &CodePlacementOptID)
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return applyDisable(TargetID, DisableCodePlace);
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if (StandardID == &StackSlotColoringID)
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return applyDisable(TargetID, DisableSSC);
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if (StandardID == &DeadMachineInstructionElimID)
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return applyDisable(TargetID, DisableMachineDCE);
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if (StandardID == &MachineLICMID)
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return applyDisable(TargetID, DisableMachineLICM);
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if (StandardID == &MachineCSEID)
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return applyDisable(TargetID, DisableMachineCSE);
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if (StandardID == &MachineSchedulerID)
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return applyOverride(TargetID, EnableMachineSched, StandardID);
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if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
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return applyDisable(TargetID, DisablePostRAMachineLICM);
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if (StandardID == &MachineSinkingID)
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return applyDisable(TargetID, DisableMachineSink);
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if (StandardID == &MachineCopyPropagationID)
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return applyDisable(TargetID, DisableCopyProp);
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return TargetID;
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}
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//===---------------------------------------------------------------------===//
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/// TargetPassConfig
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//===---------------------------------------------------------------------===//
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INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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"Target Pass Configuration", false, false)
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char TargetPassConfig::ID = 0;
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static char NoPassIDAnchor = 0;
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char &llvm::NoPassID = NoPassIDAnchor;
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// Pseudo Pass IDs.
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char TargetPassConfig::EarlyTailDuplicateID = 0;
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char TargetPassConfig::PostRAMachineLICMID = 0;
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namespace llvm {
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class PassConfigImpl {
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public:
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// List of passes explicitly substituted by this target. Normally this is
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// empty, but it is a convenient way to suppress or replace specific passes
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// that are part of a standard pass pipeline without overridding the entire
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// pipeline. This mechanism allows target options to inherit a standard pass's
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// user interface. For example, a target may disable a standard pass by
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// default by substituting NoPass, and the user may still enable that standard
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// pass with an explicit command line option.
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DenseMap<AnalysisID,AnalysisID> TargetPasses;
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/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
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/// is inserted after each instance of the first one.
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SmallVector<std::pair<AnalysisID, AnalysisID>, 4> InsertedPasses;
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};
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} // namespace llvm
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {
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delete Impl;
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}
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
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DisableVerify(false),
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EnableTailMerge(true) {
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Impl = new PassConfigImpl();
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// Register all target independent codegen passes to activate their PassIDs,
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// including this pass itself.
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initializeCodeGen(*PassRegistry::getPassRegistry());
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// Substitute Pseudo Pass IDs for real ones.
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substitutePass(EarlyTailDuplicateID, TailDuplicateID);
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substitutePass(PostRAMachineLICMID, MachineLICMID);
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// Temporarily disable experimental passes.
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substitutePass(MachineSchedulerID, NoPassID);
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}
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/// Insert InsertedPassID pass after TargetPassID.
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void TargetPassConfig::insertPass(const char &TargetPassID,
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const char &InsertedPassID) {
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assert(&TargetPassID != &InsertedPassID && "Insert a pass after itself!");
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std::pair<AnalysisID, AnalysisID> P(&TargetPassID, &InsertedPassID);
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Impl->InsertedPasses.push_back(P);
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}
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/// createPassConfig - Create a pass configuration object to be used by
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/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
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///
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/// Targets may override this to extend TargetPassConfig.
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TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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TargetPassConfig::TargetPassConfig()
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: ImmutablePass(ID), PM(0) {
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llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
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}
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// Helper to verify the analysis is really immutable.
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void TargetPassConfig::setOpt(bool &Opt, bool Val) {
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assert(!Initialized && "PassConfig is immutable");
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Opt = Val;
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}
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void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
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Impl->TargetPasses[&StandardID] = &TargetID;
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}
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AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
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DenseMap<AnalysisID, AnalysisID>::const_iterator
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I = Impl->TargetPasses.find(ID);
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if (I == Impl->TargetPasses.end())
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return ID;
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return I->second;
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}
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/// Add a CodeGen pass at this point in the pipeline after checking for target
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/// and command line overrides.
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AnalysisID TargetPassConfig::addPass(char &ID) {
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assert(!Initialized && "PassConfig is immutable");
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AnalysisID TargetID = getPassSubstitution(&ID);
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AnalysisID FinalID = overridePass(&ID, TargetID);
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if (FinalID == &NoPassID)
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return FinalID;
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Pass *P = Pass::createPass(FinalID);
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if (!P)
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llvm_unreachable("Pass ID not registered");
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PM->add(P);
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// Add the passes after the pass P if there is any.
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for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
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I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
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I != E; ++I) {
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if ((*I).first == &ID) {
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assert((*I).second && "Illegal Pass ID!");
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Pass *NP = Pass::createPass((*I).second);
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assert(NP && "Pass ID not registered");
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PM->add(NP);
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}
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}
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return FinalID;
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}
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void TargetPassConfig::printAndVerify(const char *Banner) const {
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if (TM->shouldPrintMachineCode())
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PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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PM->add(createMachineVerifierPass(Banner));
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}
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/// Add common target configurable passes that perform LLVM IR to IR transforms
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/// following machine independent optimization.
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void TargetPassConfig::addIRPasses() {
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// Basic AliasAnalysis support.
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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PM->add(createTypeBasedAliasAnalysisPass());
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PM->add(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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PM->add(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
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PM->add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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}
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PM->add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM->add(createUnreachableBlockEliminationPass());
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}
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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void TargetPassConfig::addISelPrepare() {
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if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
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PM->add(createCodeGenPreparePass(getTargetLowering()));
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PM->add(createStackProtectorPass(getTargetLowering()));
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addPreISel();
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if (PrintISelInput)
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PM->add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&dbgs()));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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PM->add(createVerifierPass());
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}
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/// Add the complete set of target-independent postISel code generator passes.
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///
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/// This can be read as the standard order of major LLVM CodeGen stages. Stages
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/// with nontrivial configuration or multiple passes are broken out below in
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/// add%Stage routines.
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///
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/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
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/// addPre/Post methods with empty header implementations allow injecting
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/// target-specific fixups just before or after major stages. Additionally,
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/// targets have the flexibility to change pass order within a stage by
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/// overriding default implementation of add%Stage routines below. Each
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/// technique has maintainability tradeoffs because alternate pass orders are
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/// not well supported. addPre/Post works better if the target pass is easily
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/// tied to a common pass. But if it has subtle dependencies on multiple passes,
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/// the target should override the stage instead.
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///
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/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
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/// before/after any target-independent pass. But it's currently overkill.
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void TargetPassConfig::addMachinePasses() {
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// Print the instruction selected machine code...
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printAndVerify("After Instruction Selection");
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// Insert a machine instr printer pass after the specified pass.
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// If -print-machineinstrs specified, print machineinstrs after all passes.
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if (StringRef(PrintMachineInstrs.getValue()).equals(""))
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TM->Options.PrintMachineCode = true;
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else if (!StringRef(PrintMachineInstrs.getValue())
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.equals("option-unspecified")) {
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const PassRegistry *PR = PassRegistry::getPassRegistry();
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const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
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const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs"));
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assert (TPI && IPI && "Pass ID not registered!");
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const char *TID = (char *)(TPI->getTypeInfo());
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const char *IID = (char *)(IPI->getTypeInfo());
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insertPass(*TID, *IID);
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}
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// Expand pseudo-instructions emitted by ISel.
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addPass(ExpandISelPseudosID);
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// Add passes that optimize machine instructions in SSA form.
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if (getOptLevel() != CodeGenOpt::None) {
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addMachineSSAOptimization();
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}
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else {
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// If the target requests it, assign local variables to stack slots relative
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// to one another and simplify frame index references where possible.
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addPass(LocalStackSlotAllocationID);
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}
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// Run pre-ra passes.
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if (addPreRegAlloc())
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printAndVerify("After PreRegAlloc passes");
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// Run register allocation and passes that are tightly coupled with it,
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// including phi elimination and scheduling.
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if (getOptimizeRegAlloc())
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addOptimizedRegAlloc(createRegAllocPass(true));
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else
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addFastRegAlloc(createRegAllocPass(false));
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// Run post-ra passes.
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if (addPostRegAlloc())
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printAndVerify("After PostRegAlloc passes");
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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addPass(PrologEpilogCodeInserterID);
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printAndVerify("After PrologEpilogCodeInserter");
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/// Add passes that optimize machine instructions after register allocation.
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if (getOptLevel() != CodeGenOpt::None)
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addMachineLateOptimization();
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// Expand pseudo instructions before second scheduling pass.
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addPass(ExpandPostRAPseudosID);
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printAndVerify("After ExpandPostRAPseudos");
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// Run pre-sched2 passes.
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if (addPreSched2())
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printAndVerify("After PreSched2 passes");
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// Second pass scheduler.
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(PostRASchedulerID);
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printAndVerify("After PostRAScheduler");
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}
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// GC
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addPass(GCMachineCodeAnalysisID);
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if (PrintGCInfo)
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PM->add(createGCInfoPrinter(dbgs()));
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// Basic block placement.
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if (getOptLevel() != CodeGenOpt::None)
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addBlockPlacement();
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if (addPreEmitPass())
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printAndVerify("After PreEmit passes");
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}
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/// Add passes that optimize machine instructions in SSA form.
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|
void TargetPassConfig::addMachineSSAOptimization() {
|
|
// Pre-ra tail duplication.
|
|
if (addPass(EarlyTailDuplicateID) != &NoPassID)
|
|
printAndVerify("After Pre-RegAlloc TailDuplicate");
|
|
|
|
// Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
// instructions dead.
|
|
addPass(OptimizePHIsID);
|
|
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
// to one another and simplify frame index references where possible.
|
|
addPass(LocalStackSlotAllocationID);
|
|
|
|
// With optimization, dead code should already be eliminated. However
|
|
// there is one known exception: lowered code for arguments that are only
|
|
// used by tail calls, where the tail calls reuse the incoming stack
|
|
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
addPass(DeadMachineInstructionElimID);
|
|
printAndVerify("After codegen DCE pass");
|
|
|
|
addPass(MachineLICMID);
|
|
addPass(MachineCSEID);
|
|
addPass(MachineSinkingID);
|
|
printAndVerify("After Machine LICM, CSE and Sinking passes");
|
|
|
|
addPass(PeepholeOptimizerID);
|
|
printAndVerify("After codegen peephole optimization pass");
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Register Allocation Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
bool TargetPassConfig::getOptimizeRegAlloc() const {
|
|
switch (OptimizeRegAlloc) {
|
|
case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
|
|
case cl::BOU_TRUE: return true;
|
|
case cl::BOU_FALSE: return false;
|
|
}
|
|
llvm_unreachable("Invalid optimize-regalloc state");
|
|
}
|
|
|
|
/// RegisterRegAlloc's global Registry tracks allocator registration.
|
|
MachinePassRegistry RegisterRegAlloc::Registry;
|
|
|
|
/// A dummy default pass factory indicates whether the register allocator is
|
|
/// overridden on the command line.
|
|
static FunctionPass *useDefaultRegisterAllocator() { return 0; }
|
|
static RegisterRegAlloc
|
|
defaultRegAlloc("default",
|
|
"pick register allocator based on -O option",
|
|
useDefaultRegisterAllocator);
|
|
|
|
/// -regalloc=... command line option.
|
|
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
|
|
RegisterPassParser<RegisterRegAlloc> >
|
|
RegAlloc("regalloc",
|
|
cl::init(&useDefaultRegisterAllocator),
|
|
cl::desc("Register allocator to use"));
|
|
|
|
|
|
/// Instantiate the default register allocator pass for this target for either
|
|
/// the optimized or unoptimized allocation path. This will be added to the pass
|
|
/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
|
|
/// in the optimized case.
|
|
///
|
|
/// A target that uses the standard regalloc pass order for fast or optimized
|
|
/// allocation may still override this for per-target regalloc
|
|
/// selection. But -regalloc=... always takes precedence.
|
|
FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
|
|
if (Optimized)
|
|
return createGreedyRegisterAllocator();
|
|
else
|
|
return createFastRegisterAllocator();
|
|
}
|
|
|
|
/// Find and instantiate the register allocation pass requested by this target
|
|
/// at the current optimization level. Different register allocators are
|
|
/// defined as separate passes because they may require different analysis.
|
|
///
|
|
/// This helper ensures that the regalloc= option is always available,
|
|
/// even for targets that override the default allocator.
|
|
///
|
|
/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
|
|
/// this can be folded into addPass.
|
|
FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
|
|
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
|
|
|
|
// Initialize the global default.
|
|
if (!Ctor) {
|
|
Ctor = RegAlloc;
|
|
RegisterRegAlloc::setDefault(RegAlloc);
|
|
}
|
|
if (Ctor != useDefaultRegisterAllocator)
|
|
return Ctor();
|
|
|
|
// With no -regalloc= override, ask the target for a regalloc pass.
|
|
return createTargetRegisterAllocator(Optimized);
|
|
}
|
|
|
|
/// Add the minimum set of target-independent passes that are required for
|
|
/// register allocation. No coalescing or scheduling.
|
|
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
|
|
addPass(PHIEliminationID);
|
|
addPass(TwoAddressInstructionPassID);
|
|
|
|
PM->add(RegAllocPass);
|
|
printAndVerify("After Register Allocation");
|
|
}
|
|
|
|
/// Add standard target-independent passes that are tightly coupled with
|
|
/// optimized register allocation, including coalescing, machine instruction
|
|
/// scheduling, and register allocation itself.
|
|
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
|
|
// LiveVariables currently requires pure SSA form.
|
|
//
|
|
// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
|
|
// LiveVariables can be removed completely, and LiveIntervals can be directly
|
|
// computed. (We still either need to regenerate kill flags after regalloc, or
|
|
// preferably fix the scavenger to not depend on them).
|
|
addPass(LiveVariablesID);
|
|
|
|
// Add passes that move from transformed SSA into conventional SSA. This is a
|
|
// "copy coalescing" problem.
|
|
//
|
|
if (!EnableStrongPHIElim) {
|
|
// Edge splitting is smarter with machine loop info.
|
|
addPass(MachineLoopInfoID);
|
|
addPass(PHIEliminationID);
|
|
}
|
|
addPass(TwoAddressInstructionPassID);
|
|
|
|
// FIXME: Either remove this pass completely, or fix it so that it works on
|
|
// SSA form. We could modify LiveIntervals to be independent of this pass, But
|
|
// it would be even better to simply eliminate *all* IMPLICIT_DEFs before
|
|
// leaving SSA.
|
|
addPass(ProcessImplicitDefsID);
|
|
|
|
if (EnableStrongPHIElim)
|
|
addPass(StrongPHIEliminationID);
|
|
|
|
addPass(RegisterCoalescerID);
|
|
|
|
// PreRA instruction scheduling.
|
|
if (addPass(MachineSchedulerID) != &NoPassID)
|
|
printAndVerify("After Machine Scheduling");
|
|
|
|
// Add the selected register allocation pass.
|
|
PM->add(RegAllocPass);
|
|
printAndVerify("After Register Allocation");
|
|
|
|
// Finally rewrite virtual registers.
|
|
addPass(VirtRegRewriterID);
|
|
printAndVerify("After Virtual Register Rewriter");
|
|
|
|
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
|
|
// but eventually, all users of it should probably be moved to addPostRA and
|
|
// it can go away. Currently, it's the intended place for targets to run
|
|
// FinalizeMachineBundles, because passes other than MachineScheduling an
|
|
// RegAlloc itself may not be aware of bundles.
|
|
if (addFinalizeRegAlloc())
|
|
printAndVerify("After RegAlloc finalization");
|
|
|
|
// Perform stack slot coloring and post-ra machine LICM.
|
|
//
|
|
// FIXME: Re-enable coloring with register when it's capable of adding
|
|
// kill markers.
|
|
addPass(StackSlotColoringID);
|
|
|
|
// Run post-ra machine LICM to hoist reloads / remats.
|
|
//
|
|
// FIXME: can this move into MachineLateOptimization?
|
|
addPass(PostRAMachineLICMID);
|
|
|
|
printAndVerify("After StackSlotColoring and postra Machine LICM");
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Post RegAlloc Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
void TargetPassConfig::addMachineLateOptimization() {
|
|
// Branch folding must be run after regalloc and prolog/epilog insertion.
|
|
if (addPass(BranchFolderPassID) != &NoPassID)
|
|
printAndVerify("After BranchFolding");
|
|
|
|
// Tail duplication.
|
|
if (addPass(TailDuplicateID) != &NoPassID)
|
|
printAndVerify("After TailDuplicate");
|
|
|
|
// Copy propagation.
|
|
if (addPass(MachineCopyPropagationID) != &NoPassID)
|
|
printAndVerify("After copy propagation pass");
|
|
}
|
|
|
|
/// Add standard basic block placement passes.
|
|
void TargetPassConfig::addBlockPlacement() {
|
|
AnalysisID ID = &NoPassID;
|
|
if (!DisableBlockPlacement) {
|
|
// MachineBlockPlacement is a new pass which subsumes the functionality of
|
|
// CodPlacementOpt. The old code placement pass can be restored by
|
|
// disabling block placement, but eventually it will be removed.
|
|
ID = addPass(MachineBlockPlacementID);
|
|
} else {
|
|
ID = addPass(CodePlacementOptID);
|
|
}
|
|
if (ID != &NoPassID) {
|
|
// Run a separate pass to collect block placement statistics.
|
|
if (EnableBlockPlacementStats)
|
|
addPass(MachineBlockPlacementStatsID);
|
|
|
|
printAndVerify("After machine block placement.");
|
|
}
|
|
}
|