llvm-6502/lib/CodeGen
Eric Christopher 14ec6808c4 If we're only emitting line tables for a particular CU then don't add
any ranges to the list of ranges for the CU as we don't want to emit
them anyway. This ensures that we will still emit ranges if we have
a compile unit compiled with only line tables and one compiled with
full debug info requested (we'll emit for the one with full debug info).

Update testcase metadata accordingly to continue emitting ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:25:00 +00:00
..
AsmPrinter If we're only emitting line tables for a particular CU then don't add 2014-02-27 01:25:00 +00:00
SelectionDAG Add missing const 2014-02-24 21:01:18 +00:00
AggressiveAntiDepBreaker.cpp Fix the aggressive anti-dep breaker's subregister definition handling 2014-02-26 20:20:30 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h Check hint registers for interference only once before evictions 2013-12-05 21:18:40 +00:00
Analysis.cpp
AntiDepBreaker.h
BasicTargetTransformInfo.cpp Add final and owerride keywords to TargetTransformInfo's subclasses. 2014-01-24 18:22:59 +00:00
BranchFolding.cpp Add a RequireStructuredCFG Field to TargetMachine. 2013-12-07 01:49:19 +00:00
BranchFolding.h
CalcSpillWeights.cpp [block-freq] Refactor LiveInterals::getSpillWeight to use the new MachineBlockFrequencyInfo methods. 2013-12-14 00:53:32 +00:00
CallingConvLower.cpp
CMakeLists.txt [CodeGenPrepare] Move CodeGenPrepare into lib/CodeGen. 2014-02-22 00:07:45 +00:00
CodeGen.cpp [CodeGenPrepare] Move CodeGenPrepare into lib/CodeGen. 2014-02-22 00:07:45 +00:00
CodeGenPrepare.cpp [CodeGenPrepare] Fix the check of the legality of an instruction. 2014-02-22 01:06:41 +00:00
CriticalAntiDepBreaker.cpp Fix known typos 2014-01-24 17:20:08 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DFAPacketizer.cpp
DwarfEHPrepare.cpp [PM] Split DominatorTree into a concrete analysis result object which 2014-01-13 13:07:17 +00:00
EarlyIfConversion.cpp
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp Convert register liveness tracking to work on a sub-register level instead of just register units. 2013-12-14 06:52:56 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp [PM] Split DominatorTree into a concrete analysis result object which 2014-01-13 13:07:17 +00:00
IfConversion.cpp PGO branch weight: fix PR18752. 2014-02-07 00:38:56 +00:00
InlineSpiller.cpp Re-sort all of the includes with ./utils/sort_includes.py so that 2014-01-07 11:48:04 +00:00
InterferenceCache.cpp The following patch' purpose is to reduce compile time for compilation of small 2014-02-06 09:23:24 +00:00
InterferenceCache.h The following patch' purpose is to reduce compile time for compilation of small 2014-02-06 09:23:24 +00:00
IntrinsicLowering.cpp Rename some member variables from TD to DL. 2014-02-18 15:33:12 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Remove capability for polymorphic destruction from LexicalScope 2013-11-20 00:54:28 +00:00
LiveDebugVariables.cpp Remove capability for polymorphic destruction from LexicalScope 2013-11-20 00:54:28 +00:00
LiveDebugVariables.h
LiveInterval.cpp
LiveIntervalAnalysis.cpp [block-freq] Rename getEntryFrequency() -> getEntryFreq() to match getBlockFreq() in all *BlockFrequencyInfo*. 2013-12-14 02:37:38 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp Convert register liveness tracking to work on a sub-register level instead of just register units. 2013-12-14 06:52:56 +00:00
LiveRangeCalc.cpp
LiveRangeCalc.h
LiveRangeEdit.cpp CalcSpillWeights: give a better describing name to calculateSpillWeights 2013-11-11 19:04:45 +00:00
LiveRegMatrix.cpp This small change reduces compile time for small programs on targets that have 2014-02-06 08:42:01 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMBuild.txt Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
LLVMTargetMachine.cpp Make DisableIntegratedAS a TargetOption. 2014-02-21 03:13:54 +00:00
LocalStackSlotAllocation.cpp LocalStackSlotAllocation: Turn one-iteration loop into if. 2014-02-23 13:34:21 +00:00
MachineBasicBlock.cpp PGO branch weight: update edge weights in IfConverter. 2014-01-29 23:18:47 +00:00
MachineBlockFrequencyInfo.cpp [block-freq] Rename getEntryFrequency() -> getEntryFreq() to match getBlockFreq() in all *BlockFrequencyInfo*. 2013-12-14 02:37:38 +00:00
MachineBlockPlacement.cpp Add a LLVM_DUMP_METHOD macro. 2014-01-03 22:53:37 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp MachineCopyPropagation has special logic for removing COPY instructions. It will remove plain COPYs using eraseFromParent(), but if the COPY has imp-defs/imp-uses it will convert it to a KILL, to keep the imp-def around. 2014-01-22 09:12:27 +00:00
MachineCSE.cpp Disabled subregister copy coalescing during MachineCSE. 2013-12-17 19:29:36 +00:00
MachineDominators.cpp
MachineFunction.cpp Put the functionality for printing a value to a raw_ostream as an 2014-01-09 02:29:41 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp [stackprotector] Use analysis from the StackProtector pass for stack layout in PEI a nd LocalStackSlot passes. 2013-12-19 03:17:11 +00:00
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Put the functionality for printing a value to a raw_ostream as an 2014-01-09 02:29:41 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegisterInfo.cpp Re-sort all of the includes with ./utils/sort_includes.py so that 2014-01-07 11:48:04 +00:00
MachineScheduler.cpp Fix known typos 2014-01-24 17:20:08 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp
MachineVerifier.cpp Replace the F_Binary flag with a F_Text one. 2014-02-24 18:20:12 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Revert "Revert "Add Constant Hoisting Pass" (r200034)" 2014-01-25 02:02:55 +00:00
PeepholeOptimizer.cpp
PHIElimination.cpp Fix typo 2014-01-22 02:38:23 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Move the PostRA scheduler's fixupKills function for reuse. 2013-12-28 21:56:55 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp [Stackmaps] Move the target-independent frame index elimination for stackmaps and patchpoints into target-specific code. 2014-02-21 23:29:32 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Fix typo 2014-02-22 19:31:28 +00:00
RegAllocBase.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
RegAllocBasic.cpp CalcSpillWeights: give a better describing name to calculateSpillWeights 2013-11-11 19:04:45 +00:00
RegAllocFast.cpp
RegAllocGreedy.cpp Add a limit to the heuristic that register allocates instructions in local order. 2014-02-26 22:07:26 +00:00
RegAllocPBQP.cpp Replace the F_Binary flag with a F_Text one. 2014-02-24 18:20:12 +00:00
RegisterClassInfo.cpp Make comment more explicit. 2013-12-17 02:18:02 +00:00
RegisterCoalescer.cpp ReMat: fix overly cavalier attitude to sub-register indices 2014-01-16 12:29:55 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Fix formatting introduced in r200941 2014-02-09 09:49:29 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp Fix known typos 2014-01-24 17:20:08 +00:00
ScheduleDAGInstrs.cpp Indent this continued line. 2014-02-25 00:43:21 +00:00
ScheduleDAGPrinter.cpp Put the functionality for printing a value to a raw_ostream as an 2014-01-09 02:29:41 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
SjLjEHPrepare.cpp CodeGen: Stop treating vectors as aggregates 2014-01-21 22:46:46 +00:00
SlotIndexes.cpp
Spiller.cpp Replacing HUGE_VALF with llvm::huge_valf in order to work around a warning triggered in MSVC 12. 2013-11-13 00:15:44 +00:00
Spiller.h
SpillPlacement.cpp [block-freq] Rename getEntryFrequency() -> getEntryFreq() to match getBlockFreq() in all *BlockFrequencyInfo*. 2013-12-14 02:37:38 +00:00
SpillPlacement.h [block-freq] Store MBFI as a field on SpillPlacement so we can access it to get the entry frequency while processing data. 2013-12-14 00:25:47 +00:00
SplitKit.cpp
SplitKit.h
StackColoring.cpp Disable the use of TBAA when using AA in CodeGen 2014-01-25 19:24:54 +00:00
StackMapLivenessAnalysis.cpp [Stackmap] Liveness Analysis Pass 2013-12-14 06:53:06 +00:00
StackMaps.cpp [Stackmaps] Cleanup code. No functional change intended. 2014-02-10 23:30:26 +00:00
StackProtector.cpp Checked return warning from coverity 2014-01-21 10:24:35 +00:00
StackSlotColoring.cpp [block-freq] Refactor LiveInterals::getSpillWeight to use the new MachineBlockFrequencyInfo methods. 2013-12-14 00:53:32 +00:00
TailDuplication.cpp Pass edges weights to MachineBasicBlock::addSuccessor in TailDuplicatePass to 2014-02-12 18:09:18 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Remove redundant fold call introduced in r195944. Thanks very much to Juergen 2014-01-02 19:38:41 +00:00
TargetLoweringBase.cpp move getNameWithPrefix and getSymbol to TargetMachine. 2014-02-19 20:30:41 +00:00
TargetLoweringObjectFileImpl.cpp move getNameWithPrefix and getSymbol to TargetMachine. 2014-02-19 20:30:41 +00:00
TargetOptionsImpl.cpp Re-sort all of the includes with ./utils/sort_includes.py so that 2014-01-07 11:48:04 +00:00
TargetRegisterInfo.cpp
TargetSchedule.cpp
TwoAddressInstructionPass.cpp Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies. 2013-12-17 04:50:45 +00:00
UnreachableBlockElim.cpp [PM] Split DominatorTree into a concrete analysis result object which 2014-01-13 13:07:17 +00:00
VirtRegMap.cpp Keep the link register for uwtable. 2014-02-25 16:57:28 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.