mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bfa4a373f4
Adds missing memory instruction variants to AVX false dependency breaking handling. (SSE was handled in r224246) Differential Revision: http://reviews.llvm.org/D6780 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224900 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
6.8 KiB
LLVM
202 lines
6.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
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define double @t1(float* nocapture %x) nounwind readonly ssp {
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entry:
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; SSE-LABEL: t1:
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; SSE: movss ([[A0:%rdi|%rcx]]), %xmm0
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; SSE: cvtss2sd %xmm0, %xmm0
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%0 = load float* %x, align 4
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%1 = fpext float %0 to double
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ret double %1
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}
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define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
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entry:
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; SSE-LABEL: t2:
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; SSE: cvtsd2ss ([[A0]]), %xmm0
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%0 = load double* %x, align 8
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%1 = fptrunc double %0 to float
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ret float %1
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}
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define float @squirtf(float* %x) nounwind {
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entry:
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; SSE-LABEL: squirtf:
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; SSE: movss ([[A0]]), %xmm0
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; SSE: sqrtss %xmm0, %xmm0
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%z = load float* %x
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%t = call float @llvm.sqrt.f32(float %z)
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ret float %t
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}
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define double @squirt(double* %x) nounwind {
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entry:
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; SSE-LABEL: squirt:
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; SSE: movsd ([[A0]]), %xmm0
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; SSE: sqrtsd %xmm0, %xmm0
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%z = load double* %x
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%t = call double @llvm.sqrt.f64(double %z)
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ret double %t
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}
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define float @squirtf_size(float* %x) nounwind optsize {
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entry:
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; SSE-LABEL: squirtf_size:
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; SSE: sqrtss ([[A0]]), %xmm0
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%z = load float* %x
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%t = call float @llvm.sqrt.f32(float %z)
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ret float %t
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}
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define double @squirt_size(double* %x) nounwind optsize {
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entry:
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; SSE-LABEL: squirt_size:
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; SSE: sqrtsd ([[A0]]), %xmm0
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%z = load double* %x
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%t = call double @llvm.sqrt.f64(double %z)
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ret double %t
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}
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declare float @llvm.sqrt.f32(float)
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declare double @llvm.sqrt.f64(double)
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; SSE-LABEL: loopdep1
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; SSE: for.body
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;
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; This loop contains two cvtsi2ss instructions that update the same xmm
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; register. Verify that the execution dependency fix pass breaks those
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; dependencies by inserting xorps instructions.
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;
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; If the register allocator chooses different registers for the two cvtsi2ss
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; instructions, they are still dependent on themselves.
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; SSE: xorps [[XMM1:%xmm[0-9]+]]
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; SSE: , [[XMM1]]
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; SSE: cvtsi2ssl %{{.*}}, [[XMM1]]
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; SSE: xorps [[XMM2:%xmm[0-9]+]]
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; SSE: , [[XMM2]]
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; SSE: cvtsi2ssl %{{.*}}, [[XMM2]]
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;
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define float @loopdep1(i32 %m) nounwind uwtable readnone ssp {
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entry:
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%tobool3 = icmp eq i32 %m, 0
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br i1 %tobool3, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%m.addr.07 = phi i32 [ %dec, %for.body ], [ %m, %entry ]
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%s1.06 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
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%s2.05 = phi float [ %add2, %for.body ], [ 0.000000e+00, %entry ]
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%n.04 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
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%conv = sitofp i32 %n.04 to float
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%add = fadd float %s1.06, %conv
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%conv1 = sitofp i32 %m.addr.07 to float
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%add2 = fadd float %s2.05, %conv1
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%inc = add nsw i32 %n.04, 1
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%dec = add nsw i32 %m.addr.07, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%s1.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
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%s2.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add2, %for.body ]
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%sub = fsub float %s1.0.lcssa, %s2.0.lcssa
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ret float %sub
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}
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; rdar:15221834 False AVX register dependencies cause 5x slowdown on
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; flops-6. Make sure the unused register read by vcvtsi2sdq is zeroed
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; to avoid cyclic dependence on a write to the same register in a
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; previous iteration.
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; AVX-LABEL: loopdep2:
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; AVX-LABEL: %loop
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; AVX: vxorps %[[REG:xmm.]], %{{xmm.}}, %{{xmm.}}
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; AVX: vcvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]], %{{xmm.}}
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; SSE-LABEL: loopdep2:
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; SSE-LABEL: %loop
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; SSE: xorps %[[REG:xmm.]], %[[REG]]
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; SSE: cvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]]
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define i64 @loopdep2(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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%fi = sitofp i64 %i to double
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%vy = load double* %y
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%fipy = fadd double %fi, %vy
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%iipy = fptosi double %fipy to i64
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%s2 = add i64 %s1, %iipy
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%inc = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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}
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; This loop contains a cvtsi2sd instruction that has a loop-carried
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; false dependency on an xmm that is modified by other scalar instructions
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; that follow it in the loop. Additionally, the source of convert is a
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; memory operand. Verify the execution dependency fix pass breaks this
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; dependency by inserting a xor before the convert.
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@x = common global [1024 x double] zeroinitializer, align 16
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@y = common global [1024 x double] zeroinitializer, align 16
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@z = common global [1024 x double] zeroinitializer, align 16
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@w = common global [1024 x double] zeroinitializer, align 16
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@v = common global [1024 x i32] zeroinitializer, align 16
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define void @loopdep3() {
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entry:
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %for.inc14, %entry
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%i.025 = phi i32 [ 0, %entry ], [ %inc15, %for.inc14 ]
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br label %for.body3
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for.body3:
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%indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ]
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%arrayidx = getelementptr inbounds [1024 x i32]* @v, i64 0, i64 %indvars.iv
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%0 = load i32* %arrayidx, align 4
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%conv = sitofp i32 %0 to double
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%arrayidx5 = getelementptr inbounds [1024 x double]* @x, i64 0, i64 %indvars.iv
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%1 = load double* %arrayidx5, align 8
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%mul = fmul double %conv, %1
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%arrayidx7 = getelementptr inbounds [1024 x double]* @y, i64 0, i64 %indvars.iv
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%2 = load double* %arrayidx7, align 8
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%mul8 = fmul double %mul, %2
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%arrayidx10 = getelementptr inbounds [1024 x double]* @z, i64 0, i64 %indvars.iv
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%3 = load double* %arrayidx10, align 8
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%mul11 = fmul double %mul8, %3
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%arrayidx13 = getelementptr inbounds [1024 x double]* @w, i64 0, i64 %indvars.iv
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store double %mul11, double* %arrayidx13, align 8
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond, label %for.inc14, label %for.body3
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for.inc14: ; preds = %for.body3
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%inc15 = add nsw i32 %i.025, 1
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%exitcond26 = icmp eq i32 %inc15, 100000
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br i1 %exitcond26, label %for.end16, label %for.cond1.preheader
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for.end16: ; preds = %for.inc14
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ret void
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;SSE-LABEL:@loopdep3
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;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
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;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: movsd [[XMM0]],
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;AVX-LABEL:@loopdep3
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;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
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;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmovsd [[XMM0]],
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}
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