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https://github.com/c64scene-ar/llvm-6502.git
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d7d003c2b7
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.1 KiB
LLVM
74 lines
2.1 KiB
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s
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%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
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%struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
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@stmt_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=1]
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; This should just not crash.
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define void @test1() nounwind {
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entry:
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br i1 true, label %cond_true, label %cond_next
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cond_true: ; preds = %entry
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%new_size.0.i = select i1 false, i32 0, i32 0 ; <i32> [#uses=1]
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%tmp.i = load i32* bitcast (i8* getelementptr (%struct.obstack* @stmt_obstack, i32 0, i32 10) to i32*) ; <i32> [#uses=1]
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%tmp.i.upgrd.1 = trunc i32 %tmp.i to i8 ; <i8> [#uses=1]
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%tmp21.i = and i8 %tmp.i.upgrd.1, 1 ; <i8> [#uses=1]
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%tmp22.i = icmp eq i8 %tmp21.i, 0 ; <i1> [#uses=1]
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br i1 %tmp22.i, label %cond_false30.i, label %cond_true23.i
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cond_true23.i: ; preds = %cond_true
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ret void
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cond_false30.i: ; preds = %cond_true
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%tmp35.i = tail call %struct._obstack_chunk* null( i32 %new_size.0.i ) ; <%struct._obstack_chunk*> [#uses=0]
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ret void
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cond_next: ; preds = %entry
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ret void
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}
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define i32 @test2(i16* %P, i16* %Q) nounwind {
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%A = load i16* %P, align 4 ; <i16> [#uses=11]
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%C = zext i16 %A to i32 ; <i32> [#uses=1]
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%D = and i32 %C, 255 ; <i32> [#uses=1]
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br label %L
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L:
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store i16 %A, i16* %Q
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ret i32 %D
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; CHECK: test2:
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; CHECK: movl 4(%esp), %eax
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; CHECK-NEXT: movzwl (%eax), %ecx
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}
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; rdar://10554090
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; xor in exit block will be CSE'ed and load will be folded to xor in entry.
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define i1 @test3(i32* %P, i32* %Q) nounwind {
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; CHECK: test3:
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; CHECK: movl 8(%esp), %eax
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; CHECK: xorl (%eax),
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; CHECK: j
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; CHECK-NOT: xor
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entry:
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%0 = load i32* %P, align 4
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%1 = load i32* %Q, align 4
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%2 = xor i32 %0, %1
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%3 = and i32 %2, 65535
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%4 = icmp eq i32 %3, 0
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br i1 %4, label %exit, label %land.end
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exit:
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%shr.i.i19 = xor i32 %1, %0
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%5 = and i32 %shr.i.i19, 2147418112
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%6 = icmp eq i32 %5, 0
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br label %land.end
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land.end:
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%7 = phi i1 [ %6, %exit ], [ false, %entry ]
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ret i1 %7
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}
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