mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
* Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
338 B
LLVM
13 lines
338 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
|
|
; PR1012
|
|
|
|
define float @foo(float* %col.2.0) {
|
|
; CHECK: fucompi
|
|
; CHECK: fcmov
|
|
%tmp = load float* %col.2.0
|
|
%tmp16 = fcmp olt float %tmp, 0.000000e+00
|
|
%tmp20 = fsub float -0.000000e+00, %tmp
|
|
%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
|
|
ret float %iftmp.2.0
|
|
}
|