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Constant idx case is still done in tablegen but other cases are then expanded Fixes <rdar://problem/10435460> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
944 B
LLVM
27 lines
944 B
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+sse41
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.0.0"
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define i64 @__builtin_ia32_vec_ext_v2di(<2 x i64> %a, i32 %i) nounwind {
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%1 = alloca <2 x i64>, align 16
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%2 = alloca i32, align 4
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store <2 x i64> %a, <2 x i64>* %1, align 16
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store i32 %i, i32* %2, align 4
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%3 = load <2 x i64>* %1, align 16
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%4 = load i32* %2, align 4
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%5 = extractelement <2 x i64> %3, i32 %4
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ret i64 %5
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}
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define <2 x i64> @__builtin_ia32_vec_int_v2di(<2 x i64> %a, i32 %i) nounwind {
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%1 = alloca <2 x i64>, align 16
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%2 = alloca i32, align 4
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store <2 x i64> %a, <2 x i64>* %1, align 16
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store i32 %i, i32* %2, align 4
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%3 = load <2 x i64>* %1, align 16
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%4 = load i32* %2, align 4
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%5 = insertelement <2 x i64> %3, i64 1, i32 %4
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ret <2 x i64> %5
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}
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