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8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
171 lines
5.6 KiB
LLVM
171 lines
5.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
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; SSSE3-LABEL: phaddw1:
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; SSSE3-NOT: vphaddw
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; SSSE3: phaddw
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; AVX-LABEL: phaddw1:
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; AVX: vphaddw
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define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%r = add <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3-LABEL: phaddw2:
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; SSSE3-NOT: vphaddw
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; SSSE3: phaddw
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; AVX-LABEL: phaddw2:
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; AVX: vphaddw
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define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
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%b = shufflevector <8 x i16> %y, <8 x i16> %x, <8 x i32> <i32 8, i32 11, i32 12, i32 15, i32 0, i32 3, i32 4, i32 7>
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%r = add <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3-LABEL: phaddd1:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd1:
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; AVX: vphaddd
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define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd2:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd2:
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; AVX: vphaddd
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define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
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%b = shufflevector <4 x i32> %y, <4 x i32> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd3:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd3:
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; AVX: vphaddd
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define <4 x i32> @phaddd3(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd4:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd4:
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; AVX: vphaddd
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define <4 x i32> @phaddd4(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd5:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd5:
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; AVX: vphaddd
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define <4 x i32> @phaddd5(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd6:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd6:
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; AVX: vphaddd
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define <4 x i32> @phaddd6(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phaddd7:
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; SSSE3-NOT: vphaddd
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; SSSE3: phaddd
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; AVX-LABEL: phaddd7:
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; AVX: vphaddd
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define <4 x i32> @phaddd7(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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%r = add <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phsubw1:
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; SSSE3-NOT: vphsubw
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; SSSE3: phsubw
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; AVX-LABEL: phsubw1:
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; AVX: vphsubw
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define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
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%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%r = sub <8 x i16> %a, %b
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ret <8 x i16> %r
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}
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; SSSE3-LABEL: phsubd1:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX-LABEL: phsubd1:
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; AVX: vphsubd
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define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
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%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phsubd2:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX-LABEL: phsubd2:
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; AVX: vphsubd
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define <4 x i32> @phsubd2(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phsubd3:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX-LABEL: phsubd3:
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; AVX: vphsubd
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define <4 x i32> @phsubd3(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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; SSSE3-LABEL: phsubd4:
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; SSSE3-NOT: vphsubd
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; SSSE3: phsubd
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; AVX-LABEL: phsubd4:
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; AVX: vphsubd
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define <4 x i32> @phsubd4(<4 x i32> %x) {
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%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = sub <4 x i32> %a, %b
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ret <4 x i32> %r
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}
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