mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
eb32048f80
This patch adds supports for the vector constant folding of TRUNCATE and FP_EXTEND instructions and tidies up the SINT_TO_FP and UINT_TO_FP instructions to match. It also moves the vector constant folding for the FNEG and FABS instructions to use the DAG.getNode() functionality like the other unary instructions. Differential Revision: http://reviews.llvm.org/D8593 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233224 91177308-0d34-0410-b5e6-96231b3b80d8
241 lines
7.8 KiB
LLVM
241 lines
7.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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define <4 x i32> @trunc2x2i64(<2 x i64> %a, <2 x i64> %b) {
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; SSE2-LABEL: trunc2x2i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: trunc2x2i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: trunc2x2i64:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: trunc2x2i64:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX-NEXT: retq
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entry:
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%0 = trunc <2 x i64> %a to <2 x i32>
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%1 = trunc <2 x i64> %b to <2 x i32>
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%2 = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %2
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}
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define i64 @trunc2i64(<2 x i64> %inval) {
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; SSE-LABEL: trunc2i64:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE-NEXT: movd %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: trunc2i64:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX-NEXT: vmovq %xmm0, %rax
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; AVX-NEXT: retq
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entry:
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%0 = trunc <2 x i64> %inval to <2 x i32>
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%1 = bitcast <2 x i32> %0 to i64
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ret i64 %1
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}
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define <8 x i16> @trunc2x4i32(<4 x i32> %a, <4 x i32> %b) {
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; SSE2-LABEL: trunc2x4i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: trunc2x4i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; SSSE3-NEXT: pshufb %xmm2, %xmm1
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; SSSE3-NEXT: pshufb %xmm2, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: trunc2x4i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; SSE41-NEXT: pshufb %xmm2, %xmm1
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; SSE41-NEXT: pshufb %xmm2, %xmm0
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: trunc2x4i32:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; AVX-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: retq
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entry:
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%0 = trunc <4 x i32> %a to <4 x i16>
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%1 = trunc <4 x i32> %b to <4 x i16>
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%2 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %2
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}
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; PR15524 http://llvm.org/bugs/show_bug.cgi?id=15524
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define i64 @trunc4i32(<4 x i32> %inval) {
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; SSE2-LABEL: trunc4i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: trunc4i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; SSSE3-NEXT: movd %xmm0, %rax
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: trunc4i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; SSE41-NEXT: movd %xmm0, %rax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: trunc4i32:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; AVX-NEXT: vmovq %xmm0, %rax
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; AVX-NEXT: retq
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entry:
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%0 = trunc <4 x i32> %inval to <4 x i16>
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%1 = bitcast <4 x i16> %0 to i64
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ret i64 %1
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}
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define <16 x i8> @trunc2x8i16(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: trunc2x8i16:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: packuswb %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: trunc2x8i16:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; SSSE3-NEXT: pshufb %xmm2, %xmm1
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; SSSE3-NEXT: pshufb %xmm2, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: trunc2x8i16:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; SSE41-NEXT: pshufb %xmm2, %xmm1
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; SSE41-NEXT: pshufb %xmm2, %xmm0
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: trunc2x8i16:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; AVX-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: retq
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entry:
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%0 = trunc <8 x i16> %a to <8 x i8>
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%1 = trunc <8 x i16> %b to <8 x i8>
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%2 = shufflevector <8 x i8> %0, <8 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %2
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}
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; PR15524 http://llvm.org/bugs/show_bug.cgi?id=15524
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define i64 @trunc8i16(<8 x i16> %inval) {
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; SSE2-LABEL: trunc8i16:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: trunc8i16:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; SSSE3-NEXT: movd %xmm0, %rax
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: trunc8i16:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: movd %xmm0, %rax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: trunc8i16:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; AVX-NEXT: vmovq %xmm0, %rax
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; AVX-NEXT: retq
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entry:
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%0 = trunc <8 x i16> %inval to <8 x i8>
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%1 = bitcast <8 x i8> %0 to i64
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ret i64 %1
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}
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define <16 x i8> @trunc16i64_const() {
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; SSE-LABEL: trunc16i64_const
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; SSE: # BB#0: # %entry
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: trunc16i64_const
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = trunc <16 x i64> zeroinitializer to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26>
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ret <16 x i8> %1
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}
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