llvm-6502/test/MC/ARM/neont2-cmp-encoding.s
Jim Grosbach d91f4e40e6 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03 22:31:40 +00:00

37 lines
1.6 KiB
ArmAsm

@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
.code 16
@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
vcvt.s32.f32 d16, d16
@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
vcvt.u32.f32 d16, d16
@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
vcvt.f32.s32 d16, d16
@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
vcvt.f32.u32 d16, d16
@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
vcvt.s32.f32 q8, q8
@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x07]
vcvt.u32.f32 q8, q8
@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06]
vcvt.f32.s32 q8, q8
@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x06]
vcvt.f32.u32 q8, q8
@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f]
vcvt.s32.f32 d16, d16, #1
@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0f]
vcvt.u32.f32 d16, d16, #1
@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
vcvt.f32.s32 d16, d16, #1
@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
vcvt.f32.u32 d16, d16, #1
@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0f]
vcvt.s32.f32 q8, q8, #1
@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0f]
vcvt.u32.f32 q8, q8, #1
@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
vcvt.f32.s32 q8, q8, #1
@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
vcvt.f32.u32 q8, q8, #1