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a430cb613b
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.0 KiB
LLVM
77 lines
2.0 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16
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; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32
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define void @foo() #0 {
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entry:
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ret void
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}
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; 16: .set mips16 # @foo
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; 16: .ent foo
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; 16: save {{.+}}
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; 16: restore {{.+}}
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; 16: .end foo
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; 32: .set nomips16 # @foo
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; 32: .ent foo
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; 32: .set noreorder
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; 32: .set nomacro
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; 32: .set noat
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; 32: jr $ra
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; 32: nop
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; 32: .set at
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; 32: .set macro
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; 32: .set reorder
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; 32: .end foo
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define void @nofoo() #1 {
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entry:
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ret void
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}
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; 16: .set nomips16 # @nofoo
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; 16: .ent nofoo
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; 16: .set noreorder
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; 16: .set nomacro
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; 16: .set noat
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; 16: jr $ra
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; 16: nop
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; 16: .set at
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; 16: .set macro
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; 16: .set reorder
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; 16: .end nofoo
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; 32: .set nomips16 # @nofoo
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; 32: .ent nofoo
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; 32: .set noreorder
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; 32: .set nomacro
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; 32: .set noat
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; 32: jr $ra
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; 32: nop
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; 32: .set at
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; 32: .set macro
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; 32: .set reorder
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; 32: .end nofoo
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define i32 @main() #2 {
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entry:
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ret i32 0
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}
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; 16: .set mips16 # @main
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; 16: .ent main
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; 16: save {{.+}}
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; 16: restore {{.+}}
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; 16: .end main
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; 32: .set mips16 # @main
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; 32: .ent main
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; 32: save {{.+}}
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; 32: restore {{.+}}
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; 32: .end main
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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