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648f00c2f0
reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
4.6 KiB
C++
111 lines
4.6 KiB
C++
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSINSTRUCTIONINFO_H
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#define MIPSINSTRUCTIONINFO_H
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#include "Mips.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "MipsRegisterInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "MipsGenInstrInfo.inc"
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namespace llvm {
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namespace Mips {
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned GetOppositeBranchOpc(unsigned Opc);
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}
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class MipsInstrInfo : public MipsGenInstrInfo {
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MipsTargetMachine &TM;
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bool IsN64;
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const MipsRegisterInfo RI;
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unsigned UncondBrOpc;
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public:
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explicit MipsInstrInfo(MipsTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MipsRegisterInfo &getRegisterInfo() const;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// Branch Analysis
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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private:
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void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond) const;
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public:
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx, uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc DL) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/// Insert nop instruction when hazard condition is found
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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};
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}
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#endif
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