mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a2b2200ff8
its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
1422 lines
64 KiB
TableGen
1422 lines
64 KiB
TableGen
//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips DSP ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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// ImmLeaf
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def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
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def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
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def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
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def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
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def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
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def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
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// Mips-specific dsp nodes
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def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, untyped>]>;
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def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
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SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
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def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
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SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>]>;
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class MipsDSPBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof>;
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class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
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def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
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def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
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def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
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def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
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def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
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def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
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def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
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def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
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def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
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def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
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def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
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def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
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def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
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def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
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def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
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def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
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def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
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def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
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def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
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def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
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def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
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def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
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def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
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def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
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def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
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def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
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def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
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def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
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def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
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def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
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def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
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def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
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def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
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def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
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def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
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def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
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def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
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def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
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def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
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// Flags.
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class Uses<list<Register> Regs> {
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list<Register> Uses = Regs;
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}
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class Defs<list<Register> Regs> {
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list<Register> Defs = Regs;
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}
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// Instruction encoding.
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class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
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class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
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class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
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class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
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class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
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class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
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class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
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class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
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class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
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class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
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class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
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class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
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class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
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class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
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class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
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class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
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class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
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class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
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class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
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class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
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class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
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class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
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class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
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class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
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class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
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class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
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class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
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class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
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class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
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class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
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class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
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class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
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class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
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class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
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class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
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class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
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class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
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class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
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class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
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class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
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class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
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class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
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class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
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class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
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class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
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class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
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class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
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class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
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class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
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class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
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class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
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class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
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class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
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class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
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class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
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class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
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class MFHI_ENC : MFHI_FMT<0b010000>;
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class MFLO_ENC : MFHI_FMT<0b010010>;
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class MTHI_ENC : MTHI_FMT<0b010001>;
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class MTLO_ENC : MTHI_FMT<0b010011>;
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class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
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class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
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class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
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class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
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class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
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class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
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class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
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class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
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class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
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class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
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class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
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class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
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class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
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class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
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class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
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class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
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class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
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class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
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class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
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class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
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class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
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class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
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class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
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class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
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class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
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class REPL_QB_ENC : REPL_FMT<0b00010>;
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class REPL_PH_ENC : REPL_FMT<0b01010>;
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class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
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class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
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class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
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class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
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class LWX_ENC : LX_FMT<0b00000>;
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class LHX_ENC : LX_FMT<0b00100>;
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class LBUX_ENC : LX_FMT<0b00110>;
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class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
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class INSV_ENC : INSV_FMT<0b001100>;
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
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class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
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class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
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class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
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class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
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class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
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class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
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class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
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class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
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class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
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class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
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class SHILO_ENC : SHILO_R1_FMT<0b11010>;
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class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
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class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
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class RDDSP_ENC : RDDSP_FMT<0b10010>;
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class WRDSP_ENC : WRDSP_FMT<0b10011>;
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class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
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class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
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class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
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class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
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class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
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class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
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class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
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class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
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class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
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class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
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class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
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class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
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class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
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class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
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class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
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class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
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class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
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class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
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class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
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class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
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class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
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class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
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class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
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class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
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class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
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class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
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class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
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class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
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class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
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class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
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class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
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class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
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class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
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class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
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class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
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class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
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class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
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class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
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class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
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class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
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class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
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class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
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class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
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class APPEND_ENC : APPEND_FMT<0b00000>;
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class BALIGN_ENC : APPEND_FMT<0b10000>;
|
|
class PREPEND_ENC : APPEND_FMT<0b00001>;
|
|
|
|
// Instruction desc.
|
|
class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCD,
|
|
RegisterClass RCS, RegisterClass RCT = RCS> {
|
|
dag OutOperandList = (outs RCD:$rd);
|
|
dag InOperandList = (ins RCS:$rs, RCT:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCD,
|
|
RegisterClass RCS = RCD> {
|
|
dag OutOperandList = (outs RCD:$rd);
|
|
dag InOperandList = (ins RCS:$rs);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
|
|
list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCS,
|
|
RegisterClass RCT = RCS> {
|
|
dag OutOperandList = (outs);
|
|
dag InOperandList = (ins RCS:$rs, RCT:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
|
|
list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCD,
|
|
RegisterClass RCS, RegisterClass RCT = RCS> {
|
|
dag OutOperandList = (outs RCD:$rd);
|
|
dag InOperandList = (ins RCS:$rs, RCT:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCT,
|
|
RegisterClass RCS = RCT> {
|
|
dag OutOperandList = (outs RCT:$rt);
|
|
dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
|
|
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
|
|
list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
|
|
InstrItinClass Itinerary = itin;
|
|
string Constraints = "$src = $rt";
|
|
}
|
|
|
|
class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCD,
|
|
RegisterClass RCT = RCD> {
|
|
dag OutOperandList = (outs RCD:$rd);
|
|
dag InOperandList = (ins RCT:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
|
|
list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
|
|
dag OutOperandList = (outs RC:$rd);
|
|
dag InOperandList = (ins uimm16:$imm);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
|
|
list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RC> {
|
|
dag OutOperandList = (outs RC:$rd);
|
|
dag InOperandList = (ins RC:$rt, CPURegs:$rs_sa);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
|
|
list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
SDPatternOperator ImmPat, InstrItinClass itin,
|
|
RegisterClass RC> {
|
|
dag OutOperandList = (outs RC:$rd);
|
|
dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
|
|
list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
|
|
InstrItinClass Itinerary = itin;
|
|
bit hasSideEffects = 1;
|
|
}
|
|
|
|
class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rd);
|
|
dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
|
|
list<dag> Pattern = [(set CPURegs:$rd,
|
|
(OpNode CPURegs:$base, CPURegs:$index))];
|
|
InstrItinClass Itinerary = itin;
|
|
bit mayLoad = 1;
|
|
}
|
|
|
|
class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin, RegisterClass RCD,
|
|
RegisterClass RCS = RCD, RegisterClass RCT = RCD> {
|
|
dag OutOperandList = (outs RCD:$rd);
|
|
dag InOperandList = (ins RCS:$rs, RCT:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
SDPatternOperator ImmOp, InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rt);
|
|
dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
|
|
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
|
|
list<dag> Pattern = [(set CPURegs:$rt,
|
|
(OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
|
|
InstrItinClass Itinerary = itin;
|
|
string Constraints = "$src = $rt";
|
|
}
|
|
|
|
class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rt);
|
|
dag InOperandList = (ins ACRegsDSP:$ac, CPURegs:$shift_rs);
|
|
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rt);
|
|
dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
|
|
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
|
|
string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac,
|
|
(OpNode immSExt6:$shift, ACRegsDSP:$acin))];
|
|
string Constraints = "$acin = $ac";
|
|
}
|
|
|
|
class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
|
|
string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac,
|
|
(OpNode CPURegs:$rs, ACRegsDSP:$acin))];
|
|
string Constraints = "$acin = $ac";
|
|
}
|
|
|
|
class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
|
|
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac,
|
|
(OpNode CPURegs:$rs, ACRegsDSP:$acin))];
|
|
string Constraints = "$acin = $ac";
|
|
}
|
|
|
|
class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rd);
|
|
dag InOperandList = (ins uimm16:$mask);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
|
|
list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs);
|
|
dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
|
|
string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
|
|
list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
|
|
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac,
|
|
(OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
|
|
string Constraints = "$acin = $ac";
|
|
}
|
|
|
|
class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode CPURegs:$rs, CPURegs:$rt))];
|
|
InstrItinClass Itinerary = itin;
|
|
int AddedComplexity = 20;
|
|
bit isCommutable = 1;
|
|
}
|
|
|
|
class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs ACRegsDSP:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
|
|
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
|
|
list<dag> Pattern = [(set ACRegsDSP:$ac,
|
|
(OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
|
|
InstrItinClass Itinerary = itin;
|
|
int AddedComplexity = 20;
|
|
string Constraints = "$acin = $ac";
|
|
}
|
|
|
|
class MFHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rd);
|
|
dag InOperandList = (ins RC:$ac);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class MTHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
|
|
dag OutOperandList = (outs RC:$ac);
|
|
dag InOperandList = (ins CPURegs:$rs);
|
|
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
|
|
InstrItinClass Itinerary = itin;
|
|
}
|
|
|
|
class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
|
|
MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> {
|
|
bit usesCustomInserter = 1;
|
|
}
|
|
|
|
class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
|
|
dag OutOperandList = (outs);
|
|
dag InOperandList = (ins brtarget:$offset);
|
|
string AsmString = !strconcat(instr_asm, "\t$offset");
|
|
InstrItinClass Itinerary = itin;
|
|
bit isBranch = 1;
|
|
bit isTerminator = 1;
|
|
bit hasDelaySlot = 1;
|
|
}
|
|
|
|
class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
|
InstrItinClass itin> {
|
|
dag OutOperandList = (outs CPURegs:$rt);
|
|
dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
|
|
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
|
|
list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
|
|
InstrItinClass Itinerary = itin;
|
|
string Constraints = "$src = $rt";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MIPS DSP Rev 1
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Addition/subtraction
|
|
class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
|
|
DSPRegs, DSPRegs>, IsCommutable,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
|
|
DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
|
|
DSPRegs, DSPRegs>, IsCommutable,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
|
|
DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
|
|
NoItinerary, CPURegs, CPURegs>,
|
|
IsCommutable, Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
|
|
NoItinerary, CPURegs, CPURegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
|
|
CPURegs, CPURegs>, IsCommutable,
|
|
Defs<[DSPCarry]>;
|
|
|
|
class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
|
|
CPURegs, CPURegs>,
|
|
IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
|
|
|
|
class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
|
|
CPURegs, CPURegs>;
|
|
|
|
class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
|
|
NoItinerary, CPURegs, DSPRegs>;
|
|
|
|
// Absolute value
|
|
class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
|
|
NoItinerary, CPURegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
// Precision reduce/expand
|
|
class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
|
|
int_mips_precrq_qb_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>;
|
|
|
|
class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
|
|
int_mips_precrq_ph_w,
|
|
NoItinerary, DSPRegs, CPURegs>;
|
|
|
|
class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
|
|
int_mips_precrq_rs_ph_w,
|
|
NoItinerary, DSPRegs,
|
|
CPURegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
|
|
int_mips_precrqu_s_qb_ph,
|
|
NoItinerary, DSPRegs,
|
|
DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
|
|
int_mips_preceq_w_phl,
|
|
NoItinerary, CPURegs, DSPRegs>;
|
|
|
|
class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
|
|
int_mips_preceq_w_phr,
|
|
NoItinerary, CPURegs, DSPRegs>;
|
|
|
|
class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
|
|
int_mips_precequ_ph_qbl,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
|
|
int_mips_precequ_ph_qbr,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
|
|
int_mips_precequ_ph_qbla,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
|
|
int_mips_precequ_ph_qbra,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
|
|
int_mips_preceu_ph_qbl,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
|
|
int_mips_preceu_ph_qbr,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
|
|
int_mips_preceu_ph_qbla,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
|
|
int_mips_preceu_ph_qbra,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
// Shift
|
|
class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
|
|
immZExt4, NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
|
|
immZExt4, NoItinerary, DSPRegs>;
|
|
|
|
class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
|
|
immZExt5, NoItinerary, CPURegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
|
|
NoItinerary, CPURegs>,
|
|
Defs<[DSPOutFlag22]>;
|
|
|
|
class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
|
|
immZExt5, NoItinerary, CPURegs>;
|
|
|
|
class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
|
|
NoItinerary, CPURegs>;
|
|
|
|
// Multiplication
|
|
class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
|
|
int_mips_muleu_s_ph_qbl,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
|
|
int_mips_muleu_s_ph_qbr,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
|
|
int_mips_muleq_s_w_phl,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag21]>;
|
|
|
|
class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
|
|
int_mips_muleq_s_w_phr,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag21]>;
|
|
|
|
class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag21]>;
|
|
|
|
class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
|
|
MipsMULSAQ_S_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
// Move from/to hi/lo.
|
|
class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>;
|
|
class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>;
|
|
class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>;
|
|
class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>;
|
|
|
|
// Dot product with accumulate/subtract
|
|
class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
|
|
|
|
class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
|
|
|
|
class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
|
|
|
|
class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
|
|
|
|
class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
|
|
class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
|
|
class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
|
|
class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
|
|
class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
|
|
class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
|
|
|
|
// Comparison
|
|
class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
|
|
int_mips_cmpu_eq_qb, NoItinerary,
|
|
DSPRegs>,
|
|
IsCommutable, Defs<[DSPCCond]>;
|
|
|
|
class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
|
|
int_mips_cmpu_lt_qb, NoItinerary,
|
|
DSPRegs>, Defs<[DSPCCond]>;
|
|
|
|
class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
|
|
int_mips_cmpu_le_qb, NoItinerary,
|
|
DSPRegs>, Defs<[DSPCCond]>;
|
|
|
|
class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
|
|
int_mips_cmpgu_eq_qb,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
IsCommutable;
|
|
|
|
class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
|
|
int_mips_cmpgu_lt_qb,
|
|
NoItinerary, CPURegs, DSPRegs>;
|
|
|
|
class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
|
|
int_mips_cmpgu_le_qb,
|
|
NoItinerary, CPURegs, DSPRegs>;
|
|
|
|
class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
|
|
NoItinerary, DSPRegs>,
|
|
IsCommutable, Defs<[DSPCCond]>;
|
|
|
|
class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPCCond]>;
|
|
|
|
class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPCCond]>;
|
|
|
|
// Misc
|
|
class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
|
|
NoItinerary, CPURegs>;
|
|
|
|
class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>;
|
|
|
|
class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
|
|
NoItinerary, DSPRegs, CPURegs>;
|
|
|
|
class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
|
|
NoItinerary, DSPRegs, CPURegs>;
|
|
|
|
class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Uses<[DSPCCond]>;
|
|
|
|
class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Uses<[DSPCCond]>;
|
|
|
|
class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
|
|
|
|
class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
|
|
|
|
class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
|
|
|
|
class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
|
|
|
|
// Extr
|
|
class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
|
|
Uses<[DSPPos]>, Defs<[DSPEFI]>;
|
|
|
|
class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
|
|
Uses<[DSPPos]>, Defs<[DSPEFI]>;
|
|
|
|
class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
|
|
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
|
|
|
|
class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
|
|
NoItinerary>,
|
|
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
|
|
|
|
class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
|
|
NoItinerary>, Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
|
|
NoItinerary>,
|
|
Defs<[DSPOutFlag23]>;
|
|
|
|
class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
|
|
|
|
class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
|
|
|
|
class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
|
|
|
|
class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
|
|
|
|
class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
|
|
|
|
class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
|
|
Uses<[DSPPos, DSPSCount]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MIPS DSP Rev 2
|
|
// Addition/subtraction
|
|
class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
|
|
DSPRegs, DSPRegs>, IsCommutable,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
|
|
DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
|
|
NoItinerary, DSPRegs>, IsCommutable;
|
|
|
|
class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
|
|
NoItinerary, DSPRegs>, IsCommutable;
|
|
|
|
class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
|
|
NoItinerary, DSPRegs>, IsCommutable;
|
|
|
|
class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
|
|
NoItinerary, DSPRegs>, IsCommutable;
|
|
|
|
class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
|
|
NoItinerary, CPURegs>, IsCommutable;
|
|
|
|
class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
|
|
NoItinerary, CPURegs>, IsCommutable;
|
|
|
|
class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
|
|
NoItinerary, CPURegs>;
|
|
|
|
class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
|
|
NoItinerary, CPURegs>;
|
|
|
|
// Comparison
|
|
class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
|
|
int_mips_cmpgdu_eq_qb,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPCCond]>;
|
|
|
|
class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
|
|
int_mips_cmpgdu_lt_qb,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
Defs<[DSPCCond]>;
|
|
|
|
class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
|
|
int_mips_cmpgdu_le_qb,
|
|
NoItinerary, CPURegs, DSPRegs>,
|
|
Defs<[DSPCCond]>;
|
|
|
|
// Absolute
|
|
class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
|
|
NoItinerary, DSPRegs>,
|
|
Defs<[DSPOutFlag20]>;
|
|
|
|
// Multiplication
|
|
class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
|
|
DSPRegs>, IsCommutable,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
|
|
NoItinerary, DSPRegs>, IsCommutable,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
|
|
NoItinerary, CPURegs>, IsCommutable,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
|
|
NoItinerary, CPURegs>, IsCommutable,
|
|
Defs<[DSPOutFlag21]>;
|
|
|
|
class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>,
|
|
IsCommutable, Defs<[DSPOutFlag21]>;
|
|
|
|
// Dot product with accumulate/subtract
|
|
class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
|
|
|
|
class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
|
|
|
|
class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
|
|
MipsDPAQX_SA_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
|
|
|
|
class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
|
|
|
|
class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
|
|
MipsDPSQX_SA_W_PH>,
|
|
Defs<[DSPOutFlag16_19]>;
|
|
|
|
class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
|
|
|
|
// Precision reduce/expand
|
|
class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
|
|
int_mips_precr_qb_ph,
|
|
NoItinerary, DSPRegs, DSPRegs>;
|
|
|
|
class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
|
|
int_mips_precr_sra_ph_w,
|
|
NoItinerary, DSPRegs,
|
|
CPURegs>;
|
|
|
|
class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
|
|
int_mips_precr_sra_r_ph_w,
|
|
NoItinerary, DSPRegs,
|
|
CPURegs>;
|
|
|
|
// Shift
|
|
class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
|
|
immZExt3, NoItinerary, DSPRegs>;
|
|
|
|
class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
|
|
NoItinerary, DSPRegs>;
|
|
|
|
// Misc
|
|
class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
|
|
NoItinerary>;
|
|
|
|
class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
|
|
NoItinerary>;
|
|
|
|
class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
|
|
NoItinerary>;
|
|
|
|
// Pseudos.
|
|
def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
|
|
NoItinerary>, Uses<[DSPPos]>;
|
|
|
|
// Instruction defs.
|
|
// MIPS DSP Rev 1
|
|
def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
|
|
def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
|
|
def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
|
|
def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
|
|
def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
|
|
def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
|
|
def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
|
|
def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
|
|
def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
|
|
def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
|
|
def ADDSC : ADDSC_ENC, ADDSC_DESC;
|
|
def ADDWC : ADDWC_ENC, ADDWC_DESC;
|
|
def MODSUB : MODSUB_ENC, MODSUB_DESC;
|
|
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
|
|
def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
|
|
def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
|
|
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
|
|
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
|
|
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
|
|
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
|
|
def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
|
|
def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
|
|
def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
|
|
def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
|
|
def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
|
|
def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
|
|
def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
|
|
def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
|
|
def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
|
|
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
|
|
def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
|
|
def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
|
|
def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
|
|
def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
|
|
def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
|
|
def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
|
|
def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
|
|
def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
|
|
def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
|
|
def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
|
|
def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
|
|
def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
|
|
def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
|
|
def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
|
|
def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
|
|
def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
|
|
def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
|
|
def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
|
|
def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
|
|
def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
|
|
def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
|
|
def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
|
|
def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
|
|
def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
|
|
def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
|
|
def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
|
|
def MFHI_DSP : MFHI_ENC, MFHI_DESC;
|
|
def MFLO_DSP : MFLO_ENC, MFLO_DESC;
|
|
def MTHI_DSP : MTHI_ENC, MTHI_DESC;
|
|
def MTLO_DSP : MTLO_ENC, MTLO_DESC;
|
|
def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
|
|
def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
|
|
def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
|
|
def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
|
|
def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
|
|
def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
|
|
def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
|
|
def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
|
|
def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
|
|
def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
|
|
def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
|
|
def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
|
|
def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
|
|
def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
|
|
def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
|
|
def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
|
|
def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
|
|
def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
|
|
def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
|
|
def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
|
|
def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
|
|
def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
|
|
def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
|
|
def BITREV : BITREV_ENC, BITREV_DESC;
|
|
def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
|
|
def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
|
|
def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
|
|
def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
|
|
def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
|
|
def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
|
|
def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
|
|
def LWX : LWX_ENC, LWX_DESC;
|
|
def LHX : LHX_ENC, LHX_DESC;
|
|
def LBUX : LBUX_ENC, LBUX_DESC;
|
|
def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
|
|
def INSV : INSV_ENC, INSV_DESC;
|
|
def EXTP : EXTP_ENC, EXTP_DESC;
|
|
def EXTPV : EXTPV_ENC, EXTPV_DESC;
|
|
def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
|
|
def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
|
|
def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
|
|
def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
|
|
def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
|
|
def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
|
|
def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
|
|
def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
|
|
def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
|
|
def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
|
|
def SHILO : SHILO_ENC, SHILO_DESC;
|
|
def SHILOV : SHILOV_ENC, SHILOV_DESC;
|
|
def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
|
|
def RDDSP : RDDSP_ENC, RDDSP_DESC;
|
|
def WRDSP : WRDSP_ENC, WRDSP_DESC;
|
|
|
|
// MIPS DSP Rev 2
|
|
let Predicates = [HasDSPR2] in {
|
|
|
|
def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
|
|
def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
|
|
def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
|
|
def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
|
|
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
|
|
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
|
|
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
|
|
def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
|
|
def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
|
|
def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
|
|
def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
|
|
def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
|
|
def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
|
|
def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
|
|
def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
|
|
def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
|
|
def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
|
|
def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
|
|
def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
|
|
def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
|
|
def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
|
|
def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
|
|
def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
|
|
def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
|
|
def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
|
|
def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
|
|
def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
|
|
def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
|
|
def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
|
|
def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
|
|
def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
|
|
def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
|
|
def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
|
|
def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
|
|
def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
|
|
def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
|
|
def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
|
|
def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
|
|
def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
|
|
def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
|
|
def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
|
|
def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
|
|
def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
|
|
def APPEND : APPEND_ENC, APPEND_DESC;
|
|
def BALIGN : BALIGN_ENC, BALIGN_DESC;
|
|
def PREPEND : PREPEND_ENC, PREPEND_DESC;
|
|
|
|
}
|
|
|
|
// Pseudos.
|
|
let isPseudo = 1 in {
|
|
// Pseudo instructions for loading and storing accumulator registers.
|
|
defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSP>;
|
|
defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
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// Pseudos for loading and storing ccond field of DSP control register.
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defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>;
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defm STORE_CCOND_DSP : StoreM<"store_ccond_dsp", DSPCC>;
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}
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// Pseudo CMP and PICK instructions.
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class PseudoCMP<Instruction RealInst> :
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PseudoDSP<(outs DSPCC:$cmp), (ins DSPRegs:$rs, DSPRegs:$rt), []>,
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PseudoInstExpansion<(RealInst DSPRegs:$rs, DSPRegs:$rt)>, NeverHasSideEffects;
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class PseudoPICK<Instruction RealInst> :
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PseudoDSP<(outs DSPRegs:$rd), (ins DSPCC:$cmp, DSPRegs:$rs, DSPRegs:$rt), []>,
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PseudoInstExpansion<(RealInst DSPRegs:$rd, DSPRegs:$rs, DSPRegs:$rt)>,
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NeverHasSideEffects;
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def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
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def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
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def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
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def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
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def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
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def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
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def PseudoPICK_PH : PseudoPICK<PICK_PH>;
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def PseudoPICK_QB : PseudoPICK<PICK_QB>;
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
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RegisterClass SrcRC> :
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DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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(COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
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def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
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def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
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def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
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def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
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def : DSPPat<(v2i16 (load addr:$a)),
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(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(v4i8 (load addr:$a)),
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(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
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def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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// Binary operations.
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class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
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Predicate Pred = HasDSP> :
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DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
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def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
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def : DSPBinPat<ADDQ_PH, v2i16, add>;
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def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
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def : DSPBinPat<SUBQ_PH, v2i16, sub>;
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def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
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def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
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def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
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def : DSPBinPat<ADDU_QB, v4i8, add>;
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def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
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def : DSPBinPat<SUBU_QB, v4i8, sub>;
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def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
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def : DSPBinPat<ADDSC, i32, addc>;
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def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
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def : DSPBinPat<ADDWC, i32, adde>;
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// Shift immediate patterns.
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class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
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SDPatternOperator Imm, Predicate Pred = HasDSP> :
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DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
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def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
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def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
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def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
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def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
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def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
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def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
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def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
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def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
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def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
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def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
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def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
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def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
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// SETCC/SELECT_CC patterns.
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class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
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(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs)),
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(ValTy ZERO)))>;
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class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
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(ValTy ZERO),
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(ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPRegs))))>;
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class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
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class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
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CondCode CC> :
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DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
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(ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
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def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
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def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
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def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
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def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
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def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
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def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
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def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
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def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
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def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
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def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
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def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
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def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
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def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
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def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
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def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
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def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
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def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
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def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
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def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
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def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
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def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
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def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
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def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
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def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
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(Instr ACRegsDSP:$ac, CPURegs:$rs)>;
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class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
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(Instr ACRegsDSP:$ac, immZExt5:$shift)>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
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// mflo/hi patterns.
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let AddedComplexity = 20 in
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def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
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// Indexed load patterns.
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class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
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DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
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(Instr i32:$base, i32:$index)>;
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let AddedComplexity = 20 in {
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def : IndexedLoadPat<zextloadi8, LBUX>;
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def : IndexedLoadPat<sextloadi16, LHX>;
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def : IndexedLoadPat<load, LWX>;
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}
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