Daniel Sanders 03fe69e90d [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values. ... Summary: The N32/N64 ABI's require that structs passed in registers are laid out such that spilling the register with 'sd' places the struct at the lowest address. For little endian this is trivial but for big-endian it requires that structs are shifted into the upper bits of the register. We also require that structs passed in registers have the 'inreg' attribute for big-endian N32/N64 to work correctly. This is because the tablegen-erated calling convention implementation only has access to the lowered form of struct arguments (one or more integers of up to 64-bits each) and is unable to determine the original type. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218451 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-25 12:15:05 +00:00
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AArch64	[FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1).	2014-09-22 21:08:53 +00:00
ARM	Fix swift-atomics testcase	2014-09-23 23:18:01 +00:00
CPP
Generic	Fix crash with an insertvalue that produces an empty object.	2014-09-20 00:10:47 +00:00
Hexagon
Inputs
Mips	[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values.	2014-09-25 12:15:05 +00:00
MSP430
NVPTX
PowerPC	[Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate	2014-09-23 20:46:49 +00:00
R600	R600/SI: Fix weird CHECK-DAG usage	2014-09-24 02:14:26 +00:00
SPARC
SystemZ
Thumb	[Thumb] Make load/store optimizer less conservative.	2014-09-24 16:35:50 +00:00
Thumb2
X86	[x86] Teach the new vector shuffle lowering to use AVX2 instructions for	2014-09-25 11:03:55 +00:00
XCore