Tom Stellard 1d8c7eb225 R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-07 19:45:45 +00:00
..
AArch64
ARM	ARM: yet another round of ARM test clean ups	2014-04-03 23:47:24 +00:00
ARM64	DAGLegalize: add last-ditch type-legalization for VSELECT.	2014-04-04 14:49:30 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math	2014-04-04 14:52:54 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Optimize away unnecessary address casts.	2014-04-03 21:18:25 +00:00
PowerPC	[PowerPC] Add a full condition code register to make the "cc" clobber work	2014-04-04 15:15:57 +00:00
R600	R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies	2014-04-07 19:45:45 +00:00
SPARC
SystemZ
Thumb	ARM: yet another round of ARM test clean ups	2014-04-03 23:47:24 +00:00
Thumb2	ARM: fix test case missed in previous roundup	2014-04-04 01:19:56 +00:00
X86	Quick fix: Triple::isOSMSVCRT() should be false for targeting cygwin.	2014-04-06 10:01:23 +00:00
XCore