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358dec5180
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
4.8 KiB
C++
128 lines
4.8 KiB
C++
//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
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VRegInfo.reserve(256);
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RegAllocHints.reserve(256);
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RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
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UsedPhysRegs.resize(TRI.getNumRegs());
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// Create the physreg use/def lists.
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PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
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memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
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}
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MachineRegisterInfo::~MachineRegisterInfo() {
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
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assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
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for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
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assert(!PhysRegUseDefLists[i] &&
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"PhysRegUseDefLists has entries after all instructions are deleted");
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#endif
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delete [] PhysRegUseDefLists;
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}
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void
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MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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unsigned VR = Reg;
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
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VRegInfo[Reg].first = RC;
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// Remove from old register class's vregs list. This may be slow but
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// fortunately this operation is rarely needed.
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std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
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std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
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VRegs.erase(I);
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// Add to new register class's vregs list.
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RegClass2VRegMap[RC->getID()].push_back(VR);
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}
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned
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MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
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assert(RegClass && "Cannot create register without RegClass!");
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// Add a reg, but keep track of whether the vector reallocated or not.
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void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
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VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
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RegAllocHints.push_back(std::make_pair(0, 0));
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if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
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// The vector reallocated, handle this now.
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HandleVRegListReallocation();
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unsigned VR = getLastVirtReg();
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RegClass2VRegMap[RegClass->getID()].push_back(VR);
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return VR;
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}
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/// HandleVRegListReallocation - We just added a virtual register to the
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/// VRegInfo info list and it reallocated. Update the use/def lists info
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/// pointers.
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void MachineRegisterInfo::HandleVRegListReallocation() {
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// The back pointers for the vreg lists point into the previous vector.
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// Update them to point to their correct slots.
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for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
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MachineOperand *List = VRegInfo[i].second;
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if (!List) continue;
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// Update the back-pointer to be accurate once more.
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List->Contents.Reg.Prev = &VRegInfo[i].second;
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}
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}
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
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assert(FromReg != ToReg && "Cannot replace a reg with itself");
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// TODO: This could be more efficient by bulk changing the operands.
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for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
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MachineOperand &O = I.getOperand();
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++I;
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O.setReg(ToReg);
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}
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}
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
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assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
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"Invalid vreg!");
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for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
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// Since we are in SSA form, we can stop at the first definition.
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if (I.getOperand().isDef())
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return &*I;
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}
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return 0;
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}
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#ifndef NDEBUG
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void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
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I.getOperand().getParent()->dump();
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}
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#endif
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