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https://github.com/c64scene-ar/llvm-6502.git
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061efcfb3e
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
3.7 KiB
C++
111 lines
3.7 KiB
C++
//===-- PTXTargetMachine.h - Define TargetMachine for PTX -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PTX specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PTX_TARGET_MACHINE_H
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#define PTX_TARGET_MACHINE_H
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#include "PTXISelLowering.h"
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#include "PTXInstrInfo.h"
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#include "PTXFrameLowering.h"
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#include "PTXSelectionDAGInfo.h"
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#include "PTXSubtarget.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class PTXTargetMachine : public LLVMTargetMachine {
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private:
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const TargetData DataLayout;
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PTXSubtarget Subtarget; // has to be initialized before FrameLowering
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PTXFrameLowering FrameLowering;
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PTXInstrInfo InstrInfo;
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PTXSelectionDAGInfo TSInfo;
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PTXTargetLowering TLInfo;
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public:
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PTXTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64Bit);
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virtual const TargetData *getTargetData() const { return &DataLayout; }
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virtual const TargetFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const PTXInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const TargetRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo(); }
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virtual const PTXTargetLowering *getTargetLowering() const {
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return &TLInfo; }
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virtual const PTXSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
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// We override this method to supply our own set of codegen passes.
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virtual bool addPassesToEmitFile(PassManagerBase &,
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formatted_raw_ostream &,
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CodeGenFileType,
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bool = true);
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// Emission of machine code through JITCodeEmitter is not supported.
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virtual bool addPassesToEmitMachineCode(PassManagerBase &,
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JITCodeEmitter &,
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bool = true) {
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return true;
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}
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// Emission of machine code through MCJIT is not supported.
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virtual bool addPassesToEmitMC(PassManagerBase &,
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MCContext *&,
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raw_ostream &,
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bool = true) {
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return true;
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}
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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}; // class PTXTargetMachine
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class PTX32TargetMachine : public PTXTargetMachine {
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virtual void anchor();
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public:
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PTX32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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}; // class PTX32TargetMachine
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class PTX64TargetMachine : public PTXTargetMachine {
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virtual void anchor();
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public:
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PTX64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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}; // class PTX32TargetMachine
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} // namespace llvm
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#endif // PTX_TARGET_MACHINE_H
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