Nadav Rotem ace0c2fad7 Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. ... When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding tables and removes the alignment restrictions from VEX-encoded instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-24 09:40:33 +00:00
..
ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430
NVPTX
PowerPC	Simplify the testcase a bit.	2012-12-20 17:47:27 +00:00
R600	R600: Expand vec4 INT <-> FP conversions	2012-12-21 16:33:24 +00:00
SI
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned.	2012-12-24 09:40:33 +00:00
XCore