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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31452 91177308-0d34-0410-b5e6-96231b3b80d8
307 lines
13 KiB
C++
307 lines
13 KiB
C++
//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAG class, which is used as the common
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// base class for SelectionDAG-based instruction scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
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#define LLVM_CODEGEN_SCHEDULEDAG_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include <set>
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namespace llvm {
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struct InstrStage;
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class MachineConstantPool;
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class MachineDebugInfo;
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class MachineInstr;
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class MRegisterInfo;
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class SelectionDAG;
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class SelectionDAGISel;
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class SSARegMap;
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class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetMachine;
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/// HazardRecognizer - This determines whether or not an instruction can be
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/// issued this cycle, and whether or not a noop needs to be inserted to handle
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/// the hazard.
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class HazardRecognizer {
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public:
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virtual ~HazardRecognizer();
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enum HazardType {
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NoHazard, // This instruction can be emitted at this cycle.
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Hazard, // This instruction can't be emitted at this cycle.
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NoopHazard // This instruction can't be emitted, and needs noops.
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};
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/// getHazardType - Return the hazard type of emitting this node. There are
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/// three possible results. Either:
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/// * NoHazard: it is legal to issue this instruction on this cycle.
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/// * Hazard: issuing this instruction would stall the machine. If some
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/// other instruction is available, issue it first.
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/// * NoopHazard: issuing this instruction would break the program. If
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/// some other instruction can be issued, do so, otherwise issue a noop.
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virtual HazardType getHazardType(SDNode *Node) {
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return NoHazard;
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}
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/// EmitInstruction - This callback is invoked when an instruction is
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/// emitted, to advance the hazard state.
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virtual void EmitInstruction(SDNode *Node) {
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}
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/// AdvanceCycle - This callback is invoked when no instructions can be
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/// issued on this cycle without a hazard. This should increment the
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/// internal state of the hazard recognizer so that previously "Hazard"
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/// instructions will now not be hazards.
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virtual void AdvanceCycle() {
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}
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// instruction stream.
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virtual void EmitNoop() {
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}
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};
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
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/// a group of nodes flagged together.
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struct SUnit {
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SDNode *Node; // Representative node.
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SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
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// Preds/Succs - The SUnits before/after us in the graph. The boolean value
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// is true if the edge is a token chain edge, false if it is a value edge.
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SmallVector<std::pair<SUnit*,bool>, 4> Preds; // All sunit predecessors.
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SmallVector<std::pair<SUnit*,bool>, 4> Succs; // All sunit successors.
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typedef SmallVector<std::pair<SUnit*,bool>, 4>::iterator pred_iterator;
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typedef SmallVector<std::pair<SUnit*,bool>, 4>::iterator succ_iterator;
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typedef SmallVector<std::pair<SUnit*,bool>, 4>::const_iterator
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const_pred_iterator;
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typedef SmallVector<std::pair<SUnit*,bool>, 4>::const_iterator
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const_succ_iterator;
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short NumPreds; // # of preds.
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short NumSuccs; // # of sucss.
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short NumPredsLeft; // # of preds not scheduled.
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short NumSuccsLeft; // # of succs not scheduled.
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short NumChainPredsLeft; // # of chain preds not scheduled.
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short NumChainSuccsLeft; // # of chain succs not scheduled.
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bool isTwoAddress : 1; // Is a two-address instruction.
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bool isCommutable : 1; // Is a commutable instruction.
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bool isPending : 1; // True once pending.
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bool isAvailable : 1; // True once available.
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bool isScheduled : 1; // True once scheduled.
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unsigned short Latency; // Node latency.
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unsigned CycleBound; // Upper/lower cycle to be scheduled at.
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unsigned Cycle; // Once scheduled, the cycle of the op.
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unsigned Depth; // Node depth;
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unsigned Height; // Node height;
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unsigned NodeNum; // Entry # of node in the node vector.
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SUnit(SDNode *node, unsigned nodenum)
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: Node(node), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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NumChainPredsLeft(0), NumChainSuccsLeft(0),
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isTwoAddress(false), isCommutable(false),
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isPending(false), isAvailable(false), isScheduled(false),
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Latency(0), CycleBound(0), Cycle(0), Depth(0), Height(0),
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NodeNum(nodenum) {}
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/// addPred - This adds the specified node as a pred of the current node if
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/// not already. This returns true if this is a new pred.
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bool addPred(SUnit *N, bool isChain) {
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for (unsigned i = 0, e = Preds.size(); i != e; ++i)
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if (Preds[i].first == N && Preds[i].second == isChain)
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return false;
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Preds.push_back(std::make_pair(N, isChain));
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return true;
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}
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/// addSucc - This adds the specified node as a succ of the current node if
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/// not already. This returns true if this is a new succ.
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bool addSucc(SUnit *N, bool isChain) {
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for (unsigned i = 0, e = Succs.size(); i != e; ++i)
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if (Succs[i].first == N && Succs[i].second == isChain)
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return false;
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Succs.push_back(std::make_pair(N, isChain));
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return true;
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}
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void dump(const SelectionDAG *G) const;
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void dumpAll(const SelectionDAG *G) const;
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};
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//===--------------------------------------------------------------------===//
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/// SchedulingPriorityQueue - This interface is used to plug different
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/// priorities computation algorithms into the list scheduler. It implements
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/// the interface of a standard priority queue, where nodes are inserted in
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/// arbitrary order and returned in priority order. The computation of the
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/// priority and the representation of the queue are totally up to the
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/// implementation to decide.
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///
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class SchedulingPriorityQueue {
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public:
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virtual ~SchedulingPriorityQueue() {}
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virtual void initNodes(std::map<SDNode*, SUnit*> &SUMap,
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std::vector<SUnit> &SUnits) = 0;
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virtual void releaseState() = 0;
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virtual bool empty() const = 0;
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virtual void push(SUnit *U) = 0;
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virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
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virtual SUnit *pop() = 0;
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/// ScheduledNode - As each node is scheduled, this method is invoked. This
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/// allows the priority function to adjust the priority of node that have
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/// already been emitted.
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virtual void ScheduledNode(SUnit *Node) {}
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};
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class ScheduleDAG {
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public:
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SelectionDAG &DAG; // DAG of the current basic block
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MachineBasicBlock *BB; // Current basic block
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo *TII; // Target instruction information
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const MRegisterInfo *MRI; // Target processor register info
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SSARegMap *RegMap; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
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// represent noop instructions.
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std::map<SDNode*, SUnit*> SUnitMap; // SDNode to SUnit mapping (n -> 1).
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std::vector<SUnit> SUnits; // The scheduling units.
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std::set<SDNode*> CommuteSet; // Nodes the should be commuted.
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ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: DAG(dag), BB(bb), TM(tm) {}
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virtual ~ScheduleDAG() {}
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/// Run - perform scheduling.
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///
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MachineBasicBlock *Run();
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(SDNode *N) {
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SUnits.push_back(SUnit(N, SUnits.size()));
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return &SUnits.back();
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}
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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void BuildSchedUnits();
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/// CalculateDepths, CalculateHeights - Calculate node depth / height.
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///
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void CalculateDepths();
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void CalculateHeights();
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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static unsigned CountOperands(SDNode *Node);
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, std::map<SDNode*, unsigned> &VRBaseMap);
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/// EmitNoop - Emit a noop instruction.
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///
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void EmitNoop();
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void EmitSchedule();
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void dumpSchedule() const;
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/// Schedule - Order nodes according to selected style.
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///
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virtual void Schedule() {}
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private:
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void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
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const TargetInstrDescriptor *II,
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std::map<SDNode*, unsigned> &VRBaseMap);
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};
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/// createBFS_DAGScheduler - This creates a simple breadth first instruction
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/// scheduler.
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ScheduleDAG *createBFS_DAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createSimpleDAGScheduler - This creates a simple two pass instruction
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/// scheduler using instruction itinerary.
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ScheduleDAG* createSimpleDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createNoItinsDAGScheduler - This creates a simple two pass instruction
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/// scheduler without using instruction itinerary.
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ScheduleDAG* createNoItinsDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createTDRRListDAGScheduler - This creates a top down register usage
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/// reduction list scheduler.
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ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createTDListDAGScheduler - This creates a top-down list scheduler with
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/// a hazard recognizer.
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ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
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SelectionDAG *DAG,
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MachineBasicBlock *BB);
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}
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#endif
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