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https://github.com/c64scene-ar/llvm-6502.git
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bbd8c33ee6
out of sync with regular cc. The only difference between the tail call cc and the normal cc was that one parameter register - R9 - was reserved for calling functions through a function pointer. After time the tail call cc has gotten out of sync with the regular cc. We can use R11 which is also caller saved but not used as parameter register for potential function pointers and remove the special tail call cc on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73233 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
12 KiB
TableGen
317 lines
12 KiB
TableGen
//===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the X86-32 and X86-64
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// architectures.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Conventions
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//===----------------------------------------------------------------------===//
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// Return-value conventions common to all X86 CC's.
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def RetCC_X86Common : CallingConv<[
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// Scalar values are returned in AX first, then DX. For i8, the ABI
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// requires the values to be in AL and AH, however this code uses AL and DL
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// instead. This is because using AH for the second register conflicts with
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// the way LLVM does multiple return values -- a return of {i16,i8} would end
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// up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
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// for functions that return two i8 values are currently expected to pack the
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// values into an i16 (which uses AX, and thus AL:AH).
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CCIfType<[i8] , CCAssignToReg<[AL, DL]>>,
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CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
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CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
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CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
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// Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
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// can only be used by ABI non-compliant code. If the target doesn't have XMM
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// registers, it won't have vector types.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
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// MMX vector types are always returned in MM0. If the target doesn't have
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// MM0, it doesn't support these vector types.
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CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
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// Long double types are always returned in ST0 (even with SSE).
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CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
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]>;
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// X86-32 C return-value convention.
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def RetCC_X86_32_C : CallingConv<[
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// The X86-32 calling convention returns FP values in ST0, unless marked
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// with "inreg" (used here to distinguish one kind of reg from another,
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// weirdly; this is really the sse-regparm calling convention) in which
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// case they use XMM0, otherwise it is the same as the common X86 calling
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// conv.
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CCIfInReg<CCIfSubtarget<"hasSSE2()",
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CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
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CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-32 FastCC return-value convention.
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def RetCC_X86_32_Fast : CallingConv<[
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// The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
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// SSE2, otherwise it is the the C calling conventions.
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// This can happen when a float, 2 x float, or 3 x float vector is split by
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// target lowering, and is returned in 1-3 sse regs.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-64 C return-value convention.
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def RetCC_X86_64_C : CallingConv<[
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// The X86-64 calling convention always returns FP values in XMM0.
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CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
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CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
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// MMX vector types are always returned in XMM0 except for v1i64 which is
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// returned in RAX. This disagrees with ABI documentation but is bug
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// compatible with gcc.
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CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
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CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-Win64 C return-value convention.
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def RetCC_X86_Win64_C : CallingConv<[
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// The X86-Win64 calling convention always returns __m64 values in RAX.
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CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
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// And FP in XMM0 only.
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CCIfType<[f32], CCAssignToReg<[XMM0]>>,
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CCIfType<[f64], CCAssignToReg<[XMM0]>>,
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// Otherwise, everything is the same as 'normal' X86-64 C CC.
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CCDelegateTo<RetCC_X86_64_C>
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]>;
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// This is the root return-value convention for the X86-32 backend.
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def RetCC_X86_32 : CallingConv<[
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// If FastCC, use RetCC_X86_32_Fast.
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CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
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// Otherwise, use RetCC_X86_32_C.
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CCDelegateTo<RetCC_X86_32_C>
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]>;
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// This is the root return-value convention for the X86-64 backend.
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def RetCC_X86_64 : CallingConv<[
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// Mingw64 and native Win64 use Win64 CC
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CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
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// Otherwise, drop to normal X86-64 CC
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CCDelegateTo<RetCC_X86_64_C>
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]>;
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// This is the return-value convention used for the entire X86 backend.
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def RetCC_X86 : CallingConv<[
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CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
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CCDelegateTo<RetCC_X86_32>
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]>;
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//===----------------------------------------------------------------------===//
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// X86-64 Argument Calling Conventions
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//===----------------------------------------------------------------------===//
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def CC_X86_64_C : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<8, 8>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in R10.
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CCIfNest<CCAssignToReg<[R10]>>,
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// The first 6 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
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CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
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// The first 8 FP/Vector arguments are passed in XMM registers.
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfSubtarget<"hasSSE1()",
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CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
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// The first 8 MMX (except for v1i64) vector arguments are passed in XMM
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// registers on Darwin.
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CCIfType<[v8i8, v4i16, v2i32, v2f32],
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CCIfSubtarget<"isTargetDarwin()",
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CCIfSubtarget<"hasSSE2()",
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CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
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// The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
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CCIfType<[v1i64],
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CCIfSubtarget<"isTargetDarwin()",
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CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Long doubles get stack slots whose size and alignment depends on the
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// subtarget.
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CCIfType<[f80], CCAssignToStack<0, 0>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
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// __m64 vectors get 8-byte stack slots that are 8-byte aligned.
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CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
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]>;
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// Calling convention used on Win64
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def CC_X86_Win64_C : CallingConv<[
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// FIXME: Handle byval stuff.
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// FIXME: Handle varargs.
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in R10.
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CCIfNest<CCAssignToReg<[R10]>>,
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// The first 4 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
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[XMM0, XMM1, XMM2, XMM3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
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[XMM0, XMM1, XMM2, XMM3]>>,
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// The first 4 FP/Vector arguments are passed in XMM registers.
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
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[RCX , RDX , R8 , R9 ]>>,
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// The first 4 MMX vector arguments are passed in GPRs.
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CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
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CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
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[XMM0, XMM1, XMM2, XMM3]>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 16-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
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// Long doubles get stack slots whose size and alignment depends on the
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// subtarget.
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CCIfType<[f80], CCAssignToStack<0, 0>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
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// __m64 vectors get 8-byte stack slots that are 16-byte aligned.
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CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
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]>;
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//===----------------------------------------------------------------------===//
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// X86 C Calling Convention
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//===----------------------------------------------------------------------===//
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/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
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/// values are spilled on the stack, and the first 4 vector values go in XMM
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/// regs.
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def CC_X86_32_Common : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// The first 3 float or double arguments, if marked 'inreg' and if the call
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// is not a vararg call and if SSE2 is available, are passed in SSE registers.
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CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
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CCIfSubtarget<"hasSSE2()",
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CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
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// The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
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// registers if the call is not a vararg call.
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CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
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CCAssignToReg<[MM0, MM1, MM2]>>>,
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// Integer/Float values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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// Doubles get 8-byte slots that are 4-byte aligned.
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CCIfType<[f64], CCAssignToStack<8, 4>>,
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// Long doubles get slots whose size depends on the subtarget.
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CCIfType<[f80], CCAssignToStack<0, 4>>,
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// The first 4 SSE vector arguments are passed in XMM registers.
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CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
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// Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
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// __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
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// passed in the parameter area.
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CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
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def CC_X86_32_C : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in ECX.
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CCIfNest<CCAssignToReg<[ECX]>>,
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// The first 3 integer arguments, if marked 'inreg' and if the call is not
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// a vararg call, are passed in integer registers.
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CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
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// Otherwise, same as everything else.
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CCDelegateTo<CC_X86_32_Common>
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]>;
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def CC_X86_32_FastCall : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in EAX.
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CCIfNest<CCAssignToReg<[EAX]>>,
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// The first 2 integer arguments are passed in ECX/EDX
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CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
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// Otherwise, same as everything else.
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CCDelegateTo<CC_X86_32_Common>
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]>;
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def CC_X86_32_FastCC : CallingConv<[
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// Handles byval parameters. Note that we can't rely on the delegation
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// to CC_X86_32_Common for this because that happens after code that
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// puts arguments in registers.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in EAX.
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CCIfNest<CCAssignToReg<[EAX]>>,
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// The first 2 integer arguments are passed in ECX/EDX
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CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
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// The first 3 float or double arguments, if the call is not a vararg
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// call and if SSE2 is available, are passed in SSE registers.
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CCIfNotVarArg<CCIfType<[f32,f64],
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CCIfSubtarget<"hasSSE2()",
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CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
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// Doubles get 8-byte slots that are 8-byte aligned.
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CCIfType<[f64], CCAssignToStack<8, 8>>,
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// Otherwise, same as everything else.
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CCDelegateTo<CC_X86_32_Common>
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]>;
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