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https://github.com/c64scene-ar/llvm-6502.git
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532a5c7dc6
abs / neg are now part of the srcN_modifiers operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218691 91177308-0d34-0410-b5e6-96231b3b80d8
1143 lines
40 KiB
C++
1143 lines
40 KiB
C++
//===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Defines an instruction selector for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUISelLowering.h" // For AMDGPUISD
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "R600InstrInfo.h"
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#include "SIDefines.h"
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#include "SIISelLowering.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Function.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// AMDGPU specific code to select AMDGPU machine instructions for
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/// SelectionDAG operations.
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class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
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// make the right decision when generating code for different targets.
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const AMDGPUSubtarget &Subtarget;
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public:
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AMDGPUDAGToDAGISel(TargetMachine &TM);
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virtual ~AMDGPUDAGToDAGISel();
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SDNode *Select(SDNode *N) override;
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const char *getPassName() const override;
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void PostprocessISelDAG() override;
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private:
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bool isInlineImmediate(SDNode *N) const;
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inline SDValue getSmallIPtrImm(unsigned Imm);
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bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
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const R600InstrInfo *TII);
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bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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// Complex pattern selectors
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bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
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bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
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static bool checkType(const Value *ptr, unsigned int addrspace);
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static bool checkPrivateAddress(const MachineMemOperand *Op);
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static bool isGlobalStore(const StoreSDNode *N);
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static bool isFlatStore(const StoreSDNode *N);
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static bool isPrivateStore(const StoreSDNode *N);
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static bool isLocalStore(const StoreSDNode *N);
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static bool isRegionStore(const StoreSDNode *N);
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bool isCPLoad(const LoadSDNode *N) const;
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bool isConstantLoad(const LoadSDNode *N, int cbID) const;
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bool isGlobalLoad(const LoadSDNode *N) const;
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bool isFlatLoad(const LoadSDNode *N) const;
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bool isParamLoad(const LoadSDNode *N) const;
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bool isPrivateLoad(const LoadSDNode *N) const;
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bool isLocalLoad(const LoadSDNode *N) const;
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bool isRegionLoad(const LoadSDNode *N) const;
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const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
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bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
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bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
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SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
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unsigned OffsetBits) const;
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bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
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bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
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SDValue &Offset1) const;
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void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
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SDValue &SOffset, SDValue &Offset, SDValue &Offen,
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SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
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SDValue &TFE) const;
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bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
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SDValue &Offset) const;
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bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
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SDValue &VAddr, SDValue &Offset,
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SDValue &SLC) const;
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bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
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SDValue &SOffset, SDValue &ImmOffset) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
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SDValue &Offset, SDValue &GLC, SDValue &SLC,
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SDValue &TFE) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
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SDValue &Offset, SDValue &GLC) const;
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SDNode *SelectAddrSpaceCast(SDNode *N);
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp, SDValue &Omod) const;
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SDNode *SelectADD_SUB_I64(SDNode *N);
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SDNode *SelectDIV_SCALE(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// \brief This pass converts a legalized DAG into a AMDGPU-specific
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// DAG, ready for instruction scheduling.
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FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
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return new AMDGPUDAGToDAGISel(TM);
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}
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AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
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}
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AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
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}
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bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
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const SITargetLowering *TL
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= static_cast<const SITargetLowering *>(getTargetLowering());
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return TL->analyzeImmediate(N) == 0;
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}
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/// \brief Determine the register class for \p OpNo
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/// \returns The register class of the virtual register that will be used for
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/// the given operand number \OpNo or NULL if the register class cannot be
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/// determined.
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const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
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unsigned OpNo) const {
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if (!N->isMachineOpcode())
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return nullptr;
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switch (N->getMachineOpcode()) {
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default: {
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const MCInstrDesc &Desc =
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TM.getSubtargetImpl()->getInstrInfo()->get(N->getMachineOpcode());
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unsigned OpIdx = Desc.getNumDefs() + OpNo;
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if (OpIdx >= Desc.getNumOperands())
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return nullptr;
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int RegClass = Desc.OpInfo[OpIdx].RegClass;
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if (RegClass == -1)
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return nullptr;
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return TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RegClass);
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}
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case AMDGPU::REG_SEQUENCE: {
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unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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const TargetRegisterClass *SuperRC =
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TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RCID);
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SDValue SubRegOp = N->getOperand(OpNo + 1);
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unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
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return TM.getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg(
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SuperRC, SubRegIdx);
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}
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}
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}
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SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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bool AMDGPUDAGToDAGISel::SelectADDRParam(
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SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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return SelectADDRParam(Addr, R1, R2);
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}
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bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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return true;
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}
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SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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unsigned int Opc = N->getOpcode();
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return nullptr; // Already selected.
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}
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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switch (Opc) {
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default: break;
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// We are selecting i64 ADD here instead of custom lower it during
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// DAG legalization, so we can fold some i64 ADDs used for address
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// calculation into the LOAD and STORE instructions.
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case ISD::ADD:
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case ISD::SUB: {
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if (N->getValueType(0) != MVT::i64 ||
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ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
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break;
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return SelectADD_SUB_I64(N);
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}
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case ISD::SCALAR_TO_VECTOR:
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case AMDGPUISD::BUILD_VERTICAL_VECTOR:
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case ISD::BUILD_VECTOR: {
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unsigned RegClassID;
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const AMDGPURegisterInfo *TRI = static_cast<const AMDGPURegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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const SIRegisterInfo *SIRI = static_cast<const SIRegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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EVT VT = N->getValueType(0);
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unsigned NumVectorElts = VT.getVectorNumElements();
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EVT EltVT = VT.getVectorElementType();
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assert(EltVT.bitsEq(MVT::i32));
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if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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bool UseVReg = true;
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for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
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U != E; ++U) {
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if (!U->isMachineOpcode()) {
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continue;
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}
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const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
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if (!RC) {
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continue;
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}
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if (SIRI->isSGPRClass(RC)) {
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UseVReg = false;
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}
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}
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switch(NumVectorElts) {
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case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
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AMDGPU::SReg_32RegClassID;
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break;
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case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
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AMDGPU::SReg_64RegClassID;
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break;
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case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
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AMDGPU::SReg_128RegClassID;
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break;
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case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
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AMDGPU::SReg_256RegClassID;
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break;
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case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
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AMDGPU::SReg_512RegClassID;
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break;
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default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
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}
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} else {
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// BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
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// that adds a 128 bits reg copy when going through TwoAddressInstructions
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// pass. We want to avoid 128 bits copies as much as possible because they
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// can't be bundled by our scheduler.
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switch(NumVectorElts) {
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case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
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case 4:
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if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
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RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
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else
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RegClassID = AMDGPU::R600_Reg128RegClassID;
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break;
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default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
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}
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}
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SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
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if (NumVectorElts == 1) {
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return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
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N->getOperand(0), RegClass);
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}
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assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
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"supported yet");
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// 16 = Max Num Vector Elements
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// 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
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// 1 = Vector Register Class
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SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
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RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
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bool IsRegSeq = true;
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unsigned NOps = N->getNumOperands();
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for (unsigned i = 0; i < NOps; i++) {
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// XXX: Why is this here?
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if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
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IsRegSeq = false;
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break;
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}
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RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
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RegSeqArgs[1 + (2 * i) + 1] =
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CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
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}
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if (NOps != NumVectorElts) {
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// Fill in the missing undef elements if this was a scalar_to_vector.
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assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
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MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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SDLoc(N), EltVT);
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for (unsigned i = NOps; i < NumVectorElts; ++i) {
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RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
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RegSeqArgs[1 + (2 * i) + 1] =
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CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
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}
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}
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if (!IsRegSeq)
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break;
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
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RegSeqArgs);
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}
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case ISD::BUILD_PAIR: {
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SDValue RC, SubReg0, SubReg1;
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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break;
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}
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if (N->getValueType(0) == MVT::i128) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
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} else if (N->getValueType(0) == MVT::i64) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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} else {
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llvm_unreachable("Unhandled value type for BUILD_PAIR");
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}
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const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
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N->getOperand(1), SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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SDLoc(N), N->getValueType(0), Ops);
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}
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case ISD::Constant:
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case ISD::ConstantFP: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
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N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
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break;
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uint64_t Imm;
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if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
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Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
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else {
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ConstantSDNode *C = cast<ConstantSDNode>(N);
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Imm = C->getZExtValue();
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}
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SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
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CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
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SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
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CurDAG->getConstant(Imm >> 32, MVT::i32));
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const SDValue Ops[] = {
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CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
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SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
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SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
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};
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
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N->getValueType(0), Ops);
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}
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case AMDGPUISD::REGISTER_LOAD: {
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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break;
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SDValue Addr, Offset;
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SelectADDRIndirect(N->getOperand(1), Addr, Offset);
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const SDValue Ops[] = {
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Addr,
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Offset,
|
|
CurDAG->getTargetConstant(0, MVT::i32),
|
|
N->getOperand(0),
|
|
};
|
|
return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
|
|
CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
|
|
Ops);
|
|
}
|
|
case AMDGPUISD::REGISTER_STORE: {
|
|
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
|
|
break;
|
|
SDValue Addr, Offset;
|
|
SelectADDRIndirect(N->getOperand(2), Addr, Offset);
|
|
const SDValue Ops[] = {
|
|
N->getOperand(1),
|
|
Addr,
|
|
Offset,
|
|
CurDAG->getTargetConstant(0, MVT::i32),
|
|
N->getOperand(0),
|
|
};
|
|
return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
|
|
CurDAG->getVTList(MVT::Other),
|
|
Ops);
|
|
}
|
|
|
|
case AMDGPUISD::BFE_I32:
|
|
case AMDGPUISD::BFE_U32: {
|
|
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
|
|
break;
|
|
|
|
// There is a scalar version available, but unlike the vector version which
|
|
// has a separate operand for the offset and width, the scalar version packs
|
|
// the width and offset into a single operand. Try to move to the scalar
|
|
// version if the offsets are constant, so that we can try to keep extended
|
|
// loads of kernel arguments in SGPRs.
|
|
|
|
// TODO: Technically we could try to pattern match scalar bitshifts of
|
|
// dynamic values, but it's probably not useful.
|
|
ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
|
|
if (!Offset)
|
|
break;
|
|
|
|
ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
|
|
if (!Width)
|
|
break;
|
|
|
|
bool Signed = Opc == AMDGPUISD::BFE_I32;
|
|
|
|
// Transformation function, pack the offset and width of a BFE into
|
|
// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
|
|
// source, bits [5:0] contain the offset and bits [22:16] the width.
|
|
|
|
uint32_t OffsetVal = Offset->getZExtValue();
|
|
uint32_t WidthVal = Width->getZExtValue();
|
|
|
|
uint32_t PackedVal = OffsetVal | WidthVal << 16;
|
|
|
|
SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
|
|
return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
|
|
SDLoc(N),
|
|
MVT::i32,
|
|
N->getOperand(0),
|
|
PackedOffsetWidth);
|
|
|
|
}
|
|
case AMDGPUISD::DIV_SCALE: {
|
|
return SelectDIV_SCALE(N);
|
|
}
|
|
case ISD::ADDRSPACECAST:
|
|
return SelectAddrSpaceCast(N);
|
|
}
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
|
|
assert(AS != 0 && "Use checkPrivateAddress instead.");
|
|
if (!Ptr)
|
|
return false;
|
|
|
|
return Ptr->getType()->getPointerAddressSpace() == AS;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
|
|
if (Op->getPseudoValue())
|
|
return true;
|
|
|
|
if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
|
|
return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
|
|
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
|
|
const Value *MemVal = N->getMemOperand()->getValue();
|
|
return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
|
|
const Value *MemVal = N->getMemOperand()->getValue();
|
|
if (CbId == -1)
|
|
return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
|
|
|
|
return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
|
|
if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
|
|
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
|
|
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
|
|
N->getMemoryVT().bitsLT(MVT::i32)) {
|
|
return true;
|
|
}
|
|
}
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
|
|
MachineMemOperand *MMO = N->getMemOperand();
|
|
if (checkPrivateAddress(N->getMemOperand())) {
|
|
if (MMO) {
|
|
const PseudoSourceValue *PSV = MMO->getPseudoValue();
|
|
if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
|
|
if (checkPrivateAddress(N->getMemOperand())) {
|
|
// Check to make sure we are not a constant pool load or a constant load
|
|
// that is marked as a private load
|
|
if (isCPLoad(N) || isConstantLoad(N, -1)) {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
const Value *MemVal = N->getMemOperand()->getValue();
|
|
if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
|
|
!checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
const char *AMDGPUDAGToDAGISel::getPassName() const {
|
|
return "AMDGPU DAG->DAG Pattern Instruction Selection";
|
|
}
|
|
|
|
#ifdef DEBUGTMP
|
|
#undef INT64_C
|
|
#endif
|
|
#undef DEBUGTMP
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Complex Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
|
|
SDValue& IntPtr) {
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
|
|
IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
|
|
SDValue& BaseReg, SDValue &Offset) {
|
|
if (!isa<ConstantSDNode>(Addr)) {
|
|
BaseReg = Addr;
|
|
Offset = CurDAG->getIntPtrConstant(0, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode *IMMOffset;
|
|
|
|
if (Addr.getOpcode() == ISD::ADD
|
|
&& (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
// If the pointer address is constant, we can move it to the offset field.
|
|
} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
SDLoc(CurDAG->getEntryNode()),
|
|
AMDGPU::ZERO, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
// Default case, no offset
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode *C;
|
|
|
|
if ((C = dyn_cast<ConstantSDNode>(Addr))) {
|
|
Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
|
|
(C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else {
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
|
|
SDLoc DL(N);
|
|
SDValue LHS = N->getOperand(0);
|
|
SDValue RHS = N->getOperand(1);
|
|
|
|
bool IsAdd = (N->getOpcode() == ISD::ADD);
|
|
|
|
SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
|
|
SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
|
|
|
|
SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
|
|
DL, MVT::i32, LHS, Sub0);
|
|
SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
|
|
DL, MVT::i32, LHS, Sub1);
|
|
|
|
SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
|
|
DL, MVT::i32, RHS, Sub0);
|
|
SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
|
|
DL, MVT::i32, RHS, Sub1);
|
|
|
|
SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
|
|
SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
|
|
|
|
|
|
unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
|
|
unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
|
|
|
|
SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
|
|
SDValue Carry(AddLo, 1);
|
|
SDNode *AddHi
|
|
= CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
|
|
SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
|
|
|
|
SDValue Args[5] = {
|
|
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
|
|
SDValue(AddLo,0),
|
|
Sub0,
|
|
SDValue(AddHi,0),
|
|
Sub1,
|
|
};
|
|
return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
|
|
}
|
|
|
|
SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
|
|
SDLoc SL(N);
|
|
EVT VT = N->getValueType(0);
|
|
|
|
assert(VT == MVT::f32 || VT == MVT::f64);
|
|
|
|
unsigned Opc
|
|
= (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
|
|
|
|
const SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
|
|
const SDValue False = CurDAG->getTargetConstant(0, MVT::i1);
|
|
SDValue Ops[] = {
|
|
Zero, // src0_modifiers
|
|
N->getOperand(0), // src0
|
|
Zero, // src1_modifiers
|
|
N->getOperand(1), // src1
|
|
Zero, // src2_modifiers
|
|
N->getOperand(2), // src2
|
|
False, // clamp
|
|
Zero // omod
|
|
};
|
|
|
|
return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
|
|
unsigned OffsetBits) const {
|
|
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
|
|
if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
|
|
(OffsetBits == 8 && !isUInt<8>(Offset)))
|
|
return false;
|
|
|
|
if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
|
|
return true;
|
|
|
|
// On Southern Islands instruction with a negative base value and an offset
|
|
// don't seem to work.
|
|
return CurDAG->SignBitIsZero(Base);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) const {
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
SDValue N0 = Addr.getOperand(0);
|
|
SDValue N1 = Addr.getOperand(1);
|
|
ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
|
|
if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
|
|
// (add n0, c0)
|
|
Base = N0;
|
|
Offset = N1;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// default case
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i16);
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset0,
|
|
SDValue &Offset1) const {
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
SDValue N0 = Addr.getOperand(0);
|
|
SDValue N1 = Addr.getOperand(1);
|
|
ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
|
|
unsigned DWordOffset0 = C1->getZExtValue() / 4;
|
|
unsigned DWordOffset1 = DWordOffset0 + 1;
|
|
// (add n0, c0)
|
|
if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
|
|
Base = N0;
|
|
Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
|
|
Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// default case
|
|
Base = Addr;
|
|
Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
|
|
Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
|
|
return true;
|
|
}
|
|
|
|
static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
|
|
return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
|
|
Ptr), 0);
|
|
}
|
|
|
|
static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
|
|
return isUInt<12>(Imm->getZExtValue());
|
|
}
|
|
|
|
void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
|
|
SDValue &VAddr, SDValue &SOffset,
|
|
SDValue &Offset, SDValue &Offen,
|
|
SDValue &Idxen, SDValue &Addr64,
|
|
SDValue &GLC, SDValue &SLC,
|
|
SDValue &TFE) const {
|
|
SDLoc DL(Addr);
|
|
|
|
GLC = CurDAG->getTargetConstant(0, MVT::i1);
|
|
SLC = CurDAG->getTargetConstant(0, MVT::i1);
|
|
TFE = CurDAG->getTargetConstant(0, MVT::i1);
|
|
|
|
Idxen = CurDAG->getTargetConstant(0, MVT::i1);
|
|
Offen = CurDAG->getTargetConstant(0, MVT::i1);
|
|
Addr64 = CurDAG->getTargetConstant(0, MVT::i1);
|
|
SOffset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
SDValue N0 = Addr.getOperand(0);
|
|
SDValue N1 = Addr.getOperand(1);
|
|
ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
|
|
|
|
if (isLegalMUBUFImmOffset(C1)) {
|
|
|
|
if (N0.getOpcode() == ISD::ADD) {
|
|
// (add (add N2, N3), C1) -> addr64
|
|
SDValue N2 = N0.getOperand(0);
|
|
SDValue N3 = N0.getOperand(1);
|
|
Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
|
|
Ptr = N2;
|
|
VAddr = N3;
|
|
Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
|
|
return;
|
|
}
|
|
|
|
// (add N0, C1) -> offset
|
|
VAddr = CurDAG->getTargetConstant(0, MVT::i32);
|
|
Ptr = N0;
|
|
Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
|
|
return;
|
|
}
|
|
}
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
// (add N0, N1) -> addr64
|
|
SDValue N0 = Addr.getOperand(0);
|
|
SDValue N1 = Addr.getOperand(1);
|
|
Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
|
|
Ptr = N0;
|
|
VAddr = N1;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i16);
|
|
return;
|
|
}
|
|
|
|
// default case -> offset
|
|
VAddr = CurDAG->getTargetConstant(0, MVT::i32);
|
|
Ptr = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i16);
|
|
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
|
|
SDValue &VAddr,
|
|
SDValue &Offset) const {
|
|
SDValue Ptr, SOffset, Offen, Idxen, Addr64, GLC, SLC, TFE;
|
|
|
|
SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
|
|
GLC, SLC, TFE);
|
|
|
|
ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
|
|
if (C->getSExtValue()) {
|
|
SDLoc DL(Addr);
|
|
SRsrc = wrapAddr64Rsrc(CurDAG, DL, Ptr);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
|
|
SDValue &VAddr, SDValue &Offset,
|
|
SDValue &SLC) const {
|
|
SLC = CurDAG->getTargetConstant(0, MVT::i1);
|
|
|
|
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
|
|
}
|
|
|
|
static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr,
|
|
uint32_t RsrcDword1, uint64_t RsrcDword2And3) {
|
|
|
|
SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
|
|
SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
|
|
if (RsrcDword1)
|
|
PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
|
|
DAG->getConstant(RsrcDword1, MVT::i32)), 0);
|
|
|
|
SDValue DataLo = DAG->getTargetConstant(
|
|
RsrcDword2And3 & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32);
|
|
SDValue DataHi = DAG->getTargetConstant(RsrcDword2And3 >> 32, MVT::i32);
|
|
|
|
const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi };
|
|
return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL,
|
|
MVT::v4i32, Ops), 0);
|
|
}
|
|
|
|
/// \brief Return a resource descriptor with the 'Add TID' bit enabled
|
|
/// The TID (Thread ID) is multipled by the stride value (bits [61:48]
|
|
/// of the resource descriptor) to create an offset, which is added to the
|
|
/// resource ponter.
|
|
static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
|
|
|
|
uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
|
|
0xffffffff; // Size
|
|
|
|
return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
|
|
SDValue &VAddr, SDValue &SOffset,
|
|
SDValue &ImmOffset) const {
|
|
|
|
SDLoc DL(Addr);
|
|
MachineFunction &MF = CurDAG->getMachineFunction();
|
|
const SIRegisterInfo *TRI =
|
|
static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
const SITargetLowering& Lowering =
|
|
*static_cast<const SITargetLowering*>(getTargetLowering());
|
|
|
|
unsigned ScratchPtrReg =
|
|
TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
|
|
unsigned ScratchOffsetReg =
|
|
TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
|
|
Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
|
|
ScratchOffsetReg, MVT::i32);
|
|
|
|
Rsrc = buildScratchRSRC(CurDAG, DL,
|
|
CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
|
|
MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64));
|
|
SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
|
|
MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
|
|
|
|
// (add n0, c1)
|
|
if (CurDAG->isBaseWithConstantOffset(Addr)) {
|
|
SDValue N1 = Addr.getOperand(1);
|
|
ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
|
|
|
|
if (isLegalMUBUFImmOffset(C1)) {
|
|
VAddr = Addr.getOperand(0);
|
|
ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// (add FI, n0)
|
|
if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
|
|
isa<FrameIndexSDNode>(Addr.getOperand(0))) {
|
|
VAddr = Addr.getOperand(1);
|
|
ImmOffset = Addr.getOperand(0);
|
|
return true;
|
|
}
|
|
|
|
// (FI)
|
|
if (isa<FrameIndexSDNode>(Addr)) {
|
|
VAddr = SDValue(CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32,
|
|
CurDAG->getConstant(0, MVT::i32)), 0);
|
|
ImmOffset = Addr;
|
|
return true;
|
|
}
|
|
|
|
// (node)
|
|
VAddr = Addr;
|
|
ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
|
|
SDValue &SOffset, SDValue &Offset,
|
|
SDValue &GLC, SDValue &SLC,
|
|
SDValue &TFE) const {
|
|
SDValue Ptr, VAddr, Offen, Idxen, Addr64;
|
|
|
|
SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
|
|
GLC, SLC, TFE);
|
|
|
|
if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
|
|
!cast<ConstantSDNode>(Idxen)->getSExtValue() &&
|
|
!cast<ConstantSDNode>(Addr64)->getSExtValue()) {
|
|
uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT |
|
|
APInt::getAllOnesValue(32).getZExtValue(); // Size
|
|
SDLoc DL(Addr);
|
|
SRsrc = buildRSRC(CurDAG, DL, Ptr, 0, Rsrc);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
|
|
SDValue &Soffset, SDValue &Offset,
|
|
SDValue &GLC) const {
|
|
SDValue SLC, TFE;
|
|
|
|
return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
|
|
}
|
|
|
|
// FIXME: This is incorrect and only enough to be able to compile.
|
|
SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
|
|
AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
|
|
SDLoc DL(N);
|
|
|
|
assert(Subtarget.hasFlatAddressSpace() &&
|
|
"addrspacecast only supported with flat address space!");
|
|
|
|
assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
|
|
ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
|
|
"Cannot cast address space to / from constant address!");
|
|
|
|
assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
|
|
ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
|
|
"Can only cast to / from flat address space!");
|
|
|
|
// The flat instructions read the address as the index of the VGPR holding the
|
|
// address, so casting should just be reinterpreting the base VGPR, so just
|
|
// insert trunc / bitcast / zext.
|
|
|
|
SDValue Src = ASC->getOperand(0);
|
|
EVT DestVT = ASC->getValueType(0);
|
|
EVT SrcVT = Src.getValueType();
|
|
|
|
unsigned SrcSize = SrcVT.getSizeInBits();
|
|
unsigned DestSize = DestVT.getSizeInBits();
|
|
|
|
if (SrcSize > DestSize) {
|
|
assert(SrcSize == 64 && DestSize == 32);
|
|
return CurDAG->getMachineNode(
|
|
TargetOpcode::EXTRACT_SUBREG,
|
|
DL,
|
|
DestVT,
|
|
Src,
|
|
CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
|
|
}
|
|
|
|
|
|
if (DestSize > SrcSize) {
|
|
assert(SrcSize == 32 && DestSize == 64);
|
|
|
|
SDValue RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
|
|
|
|
const SDValue Ops[] = {
|
|
RC,
|
|
Src,
|
|
CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
|
|
SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
|
|
CurDAG->getConstant(0, MVT::i32)), 0),
|
|
CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
|
|
};
|
|
|
|
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
|
|
SDLoc(N), N->getValueType(0), Ops);
|
|
}
|
|
|
|
assert(SrcSize == 64 && DestSize == 64);
|
|
return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
|
|
SDValue &SrcMods) const {
|
|
|
|
unsigned Mods = 0;
|
|
|
|
Src = In;
|
|
|
|
if (Src.getOpcode() == ISD::FNEG) {
|
|
Mods |= SISrcMods::NEG;
|
|
Src = Src.getOperand(0);
|
|
}
|
|
|
|
if (Src.getOpcode() == ISD::FABS) {
|
|
Mods |= SISrcMods::ABS;
|
|
Src = Src.getOperand(0);
|
|
}
|
|
|
|
SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
|
|
SDValue &SrcMods, SDValue &Clamp,
|
|
SDValue &Omod) const {
|
|
// FIXME: Handle Clamp and Omod
|
|
Clamp = CurDAG->getTargetConstant(0, MVT::i32);
|
|
Omod = CurDAG->getTargetConstant(0, MVT::i32);
|
|
|
|
return SelectVOP3Mods(In, Src, SrcMods);
|
|
}
|
|
|
|
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
|
|
const AMDGPUTargetLowering& Lowering =
|
|
*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
|
|
bool IsModified = false;
|
|
do {
|
|
IsModified = false;
|
|
// Go over all selected nodes and try to fold them a bit more
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
E = CurDAG->allnodes_end(); I != E; ++I) {
|
|
|
|
SDNode *Node = I;
|
|
|
|
MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
|
|
if (!MachineNode)
|
|
continue;
|
|
|
|
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
|
|
if (ResNode != Node) {
|
|
ReplaceUses(Node, ResNode);
|
|
IsModified = true;
|
|
}
|
|
}
|
|
CurDAG->RemoveDeadNodes();
|
|
} while (IsModified);
|
|
}
|