llvm-6502/test/CodeGen/AArch64/zero-reg.ll
Tim Northover 7bc8414ee9 Add explicit triples to AArch64 tests
Only Linux is supported at the moment, and other platforms quickly fault. As a
result these tests would fail on non-Linux hosts. It may be worth making the
tests more generic again as more platforms are supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 11:40:47 +00:00

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762 B
LLVM

; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0
define void @test_zr() {
; CHECK: test_zr:
store i32 0, i32* @var32
; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
store i64 0, i64* @var64
; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64]
ret void
; CHECK: ret
}
define void @test_sp(i32 %val) {
; CHECK: test_sp:
; Important correctness point here is that LLVM doesn't try to use xzr
; as an addressing register: "str w0, [xzr]" is not a valid A64
; instruction (0b11111 in the Rn field would mean "sp").
%addr = getelementptr i32* null, i64 0
store i32 %val, i32* %addr
; CHECK: mov x[[NULL:[0-9]+]], xzr
; CHECK: str {{w[0-9]+}}, [x[[NULL]]]
ret void
; CHECK: ret
}