mirror of
https://github.com/c64scene-ar/llvm-6502.git
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518bb53485
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
251 lines
8.3 KiB
C++
251 lines
8.3 KiB
C++
//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
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// JIT-compile bitcode to native PowerPC.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCTargetMachine.h"
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#include "PPCRelocations.h"
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#include "PPC.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace {
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class PPCCodeEmitter : public MachineFunctionPass {
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TargetMachine &TM;
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JITCodeEmitter &MCE;
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineModuleInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static char ID;
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/// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
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/// its address in the function into this pointer.
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void *MovePCtoLROffset;
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public:
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PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(&ID), TM(tm), MCE(mce) {}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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unsigned getBinaryCodeForInstr(const MachineInstr &MI);
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/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO);
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const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
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/// runOnMachineFunction - emits the given MachineFunction to memory
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///
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bool runOnMachineFunction(MachineFunction &MF);
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/// emitBasicBlock - emits the given MachineBasicBlock to memory
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///
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void emitBasicBlock(MachineBasicBlock &MBB);
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/// getValueBit - return the particular bit of Val
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///
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unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
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};
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}
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char PPCCodeEmitter::ID = 0;
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/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
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/// to the specified MCE object.
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FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
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JITCodeEmitter &JCE) {
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return new PPCCodeEmitter(TM, JCE);
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}
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bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
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do {
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MovePCtoLROffset = 0;
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MCE.startFunction(MF);
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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emitBasicBlock(*BB);
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} while (MCE.finishFunction(MF));
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return false;
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}
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void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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MCE.StartMachineBasicBlock(&MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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const MachineInstr &MI = *I;
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MCE.processDebugLoc(MI.getDebugLoc(), true);
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switch (MI.getOpcode()) {
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default:
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MCE.emitWordBE(getBinaryCodeForInstr(MI));
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break;
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case TargetOpcode::DBG_LABEL:
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case TargetOpcode::EH_LABEL:
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MCE.emitLabel(MI.getOperand(0).getImm());
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break;
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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case PPC::MovePCtoLR8:
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assert(TM.getRelocationModel() == Reloc::PIC_);
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MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
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MCE.emitWordBE(0x48000005); // bl 1
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break;
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}
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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}
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}
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unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) {
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unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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if (MO.isReg()) {
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rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
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// Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
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// register, not the register number directly.
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if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
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(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
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rv = 0x80 >> rv;
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}
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} else if (MO.isImm()) {
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rv = MO.getImm();
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} else if (MO.isGlobal() || MO.isSymbol() ||
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MO.isCPI() || MO.isJTI()) {
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unsigned Reloc = 0;
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if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin ||
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MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF ||
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MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8)
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Reloc = PPC::reloc_pcrel_bx;
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else {
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if (TM.getRelocationModel() == Reloc::PIC_) {
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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}
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switch (MI.getOpcode()) {
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default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
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case PPC::LIS:
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case PPC::LIS8:
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case PPC::ADDIS:
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case PPC::ADDIS8:
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Reloc = PPC::reloc_absolute_high; // Pointer to symbol
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break;
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case PPC::LI:
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case PPC::LI8:
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case PPC::LA:
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// Loads.
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case PPC::LBZ:
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case PPC::LBZ8:
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case PPC::LHA:
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case PPC::LHA8:
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case PPC::LHZ:
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case PPC::LHZ8:
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case PPC::LWZ:
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case PPC::LWZ8:
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case PPC::LFS:
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case PPC::LFD:
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// Stores.
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case PPC::STB:
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case PPC::STB8:
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case PPC::STH:
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case PPC::STH8:
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case PPC::STW:
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case PPC::STW8:
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case PPC::STFS:
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case PPC::STFD:
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Reloc = PPC::reloc_absolute_low;
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break;
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case PPC::LWA:
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case PPC::LD:
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case PPC::STD:
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case PPC::STD_32:
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Reloc = PPC::reloc_absolute_low_ix;
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break;
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}
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}
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MachineRelocation R;
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if (MO.isGlobal()) {
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R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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MO.getGlobal(), 0,
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isa<Function>(MO.getGlobal()));
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} else if (MO.isSymbol()) {
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R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, MO.getSymbolName(), 0);
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} else if (MO.isCPI()) {
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R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, MO.getIndex(), 0);
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} else {
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assert(MO.isJTI());
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R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, MO.getIndex(), 0);
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}
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// If in PIC mode, we need to encode the negated address of the
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// 'movepctolr' into the unrelocated field. After relocation, we'll have
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// &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
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// field, we get &gv. This doesn't happen for branch relocations, which are
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// always implicitly pc relative.
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if (TM.getRelocationModel() == Reloc::PIC_ && Reloc != PPC::reloc_pcrel_bx){
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
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}
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MCE.addRelocation(R);
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} else if (MO.isMBB()) {
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unsigned Reloc = 0;
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unsigned Opcode = MI.getOpcode();
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if (Opcode == PPC::B || Opcode == PPC::BL_Darwin ||
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Opcode == PPC::BLA_Darwin|| Opcode == PPC::BL_SVR4 ||
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Opcode == PPC::BLA_SVR4)
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Reloc = PPC::reloc_pcrel_bx;
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else // BCC instruction
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Reloc = PPC::reloc_pcrel_bcx;
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Reloc, MO.getMBB()));
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} else {
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#ifndef NDEBUG
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errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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#endif
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llvm_unreachable(0);
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}
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return rv;
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}
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#include "PPCGenCodeEmitter.inc"
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